TS68040 ATMEL Corporation, TS68040 Datasheet - Page 32

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

TS 68040
6.7.1 - Translation mechanism
Because logical-to-physical address translation is one of the most frequently executed operations of the TS 68040 MMUs,
this task has been optimized. Each MMU initiates address translation by searching for a descriptor containing the address
translation information in the ATC. If the descriptor does not reside in the ATC, then the MMU performs external bus cycles
via the bus controller to search the translation tables in physical memory. After being located, the page descriptor is loaded
into the ATC, and the address is correctly translated for the access, provided no exception conditions are encountered.
6.7.2 - Address translation cache
An integral part of the translation function previously described is the dual cache memory that stores recently used logical-
to-physical address translation information (page descriptors) for instruction and date accesses. These caches are 64-entry,
four-way, set associative. Each ATC compare the logical address of the incoming access against its entries. If one of the
entries matches, there is a hit, and the ATC sends the physical address to the bus controller, which then starts the external
bus cycle (provided there was no hit in the corresponding cache for the access).
6.7.3 - Translation tables
The translation tables of the TS 68040 have a threelevel tree structure and reside in main memory. Since only a portion of
the complete tree needs to exist at any one time, the tree structure minimizes the amount of memory necessary to set up
the tables for most programs. As shown in Figure 20, either the user root pointer or the supervisor root pointer points to
the first level table, depending on the values of the function code for an access. Table entries at the second level of the tree
(pointer tables) contain pointers to the third level (page tables). Entries in the page tables contain either page descriptors
or indirect pointers to page descriptors. The mechanism for performing table search operations uses portions of the logical
address (as indices) at each level of the search. All addresses in the translation table entries are physical addresses.
Figure 22 : Translation table structure.
There are two variations of table searches for both 4K and 8K page sizes : normal searches and indirect searches. An
indirect search differs in that the entry in the third level page table contains a pointer to a page descriptor rather than the
page descriptor itself.
Entries in the translation tables contain control and status information on addition to the physical address information. Control
bits specify write protection, limit access to supervisor only, and determine cachability of data in each memory page. Each
page descriptor also has two user-programmable bits that appear on the UPA0 and UPA1 signals during an external access
for use as address modifier bits.
A global bit can be set in each page descriptor to prevent flushing of the ATC entry for that page by some PFLUSH instruction
variants, allowing system ATC entries to remain resident during task swaps. If these special PFLUSH instructions are not
used, this bit can be user defined. The MMUs automatically maintain access history information for the pages by updating
the used (U) and modified (M) status bits.
6.7.4 - MMU instructions
The MMU instructions supported by the TS 68040 are as follows :
PFLUSH : Allows flushing of either selected ATC entries by function code and logical address or the entire ATCs.
PTEST : Takes an address and function code and searches the translation tables for the corresponding entry, which is then
loaded into the ATC. The results of the search are available in the MMU status register and are often useful in determining
the cause of a fault.
All of the TS 68040 MMU instructions are privileged and can only be executed from the supervisor mode.
32/38