SDA9257 Infineon Technologies Corporation, SDA9257 Datasheet - Page 21

• Manufacturer Part Number: SDA9257
• Description: Clock SYNC Generator
• Manufacturer: Infineon Technologies Corporation

Table 2
Output Coding in Case of CCIR 656 Format, FORMAT = 00
Step
Underflow
0
1
2
•
•
253
254
255
Overflow
V
resp. AINU, AINV
Table 2 is valid for
2.3
The clock sync generator is a phase locked loop that locks on a horizontal SYNC input
signal and generates the clock signals as well as additional control output signals.
2.3.1 Horizontal PLL (HPLL)
The input signal SYNC may be either a CVBS signal or a composite sync signal. The
polarity of the SYNC signal can be both positive or negative (
of the SYNC input pulses should not be steeper than 100 ns. The frequency of the SYNC
signal can be of normal or double line frequency (
The SYNC is clamped before A/D conversion. For DC-input signals clamping can be
disabled (
of 27 MHz.
The digital HPLL filters the signal with a cutoff frequency of 1 MHz (2 MHz for 2fh mode).
If 1fh mode is used the sampling frequency is decimated to 13.5 MHz. Following the low
pass filtering a black- and sync bottom- level measurement takes place in order to
calculate a threshold value. By means of this value the phase difference between the
HPLL output and the SYNC input pulse is determined. Using a digital PI filter an
increment is calculated from this for the Discrete Timing Oscillator (DTO). It is possible
Semiconductor Group
CY
,
V
CU,V
Clock Sync Generation
I
: ext. clamping level during clamping at
2
AINY
<
>
C-Bit CLOF). A/D conversion takes place with 7 bits and a nominal frequency
V
V
V
V
•
•
V
V
V
V
CY
CY
CY
CY
CY
CY
CY
CY
- 0.125 V
- 0.125 V
- 0.117 V
- 0.109 V
+ 1.859 V
+ 1.867 V
+ 1.875 V
+ 1.875 V
V
REFL
= 2.2 V and
AINU, AINV
<
>
•
•
V
V
V
V
V
V
V
V
CU, V
CU, V
CU, V
CU, V
CU, V
CU, V
CU, V
CU, V
+ 0.992 V
+ 0.984 V
- 1.0 V
- 1.0 V
- 0.992 V
- 0.984 V
+ 1.0 V
+ 1.0 V
V
REFH
21
= 4.2 V, xAMP = 0000
OFL
Bit
0
0
0
0
•
•
0
0
0
1
C
I
2
ext cl
C-Bit 2FH).
UFL
Bit
1
0
0
0
•
•
0
0
0
0
on channel AINY
Straight
Binary
7 65 4 3 2 10
00 0 0 00 0 1
00 0 0 00 0 1
00 0 0 00 0 1
00 0 0 00 1 0
•
•
11 1 1 11 0 1
11 1 1 11 1 0
11 1 1 11 1 0
11 1 1 11 1 0
I
2
C-Bit SYPOL). The edges
Two’s
Complement
7 6 54 3 2 1 0
10 0 0 00 0 0
10 0 0 00 0 0
10 0 0 00 0 1
10 0 0 00 1 0
•
•
01 1 1 11 0 1
01 1 1 11 1 0
01 1 1 11 1 1
01 1 1 11 1 1
SDA 9206
1999-02-10