SDA9257 Infineon Technologies Corporation, SDA9257 Datasheet - Page 42

• Manufacturer Part Number: SDA9257
• Description: Clock SYNC Generator
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.4.5 Read Mode
Status Byte 0
Bit
D7
D6
D5, D4
D3
D2 ... D0
Name
CON
THRELIM Absolute difference between the horizontal sync pulse in SYNC
FFGF, FF Identified number
POR
Function
Absolute difference between the horizontal sync pulse in SYNC
and the HPLL:
0:
1:
and the HPLL:
0:
1:
of lines per field
(refer also to timing diagram
figure 16):
< N1
> N2 and < 287
> N4
N1 to N4 depends on Control Bits VWIWI:
VWIWI1
0
0
1
1
don´t care
Status bit POR is set by power on reset or by activating the reset pin.
POR is reset after reading the status byte.
N1 and
287 and < N3
N3 and
Larger than or equal to 32 system clock cycles
Less than 32 system clock cycles
Larger than 8 system clock cycles
Less than 8 system clock cycles for 8 or more
successive lines (i.e. HPLL well locked in)
VWIWI0
0
1
0
1
N2
N4
42
N1
262
250
240
200
FFGF
0
1
0
0
1
0
N2
264
275
285
312
Status Bits
N3
312
300
290
250
FF
0
0
0
1
1
1
314
325
335
362
N4
SDA 9206
1999-02-10