SDA9257 Infineon Technologies Corporation, SDA9257 Datasheet - Page 26

• Manufacturer Part Number: SDA9257
• Description: Clock SYNC Generator
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.3.4 Miscellaneous Circuit Sections
To suppress bottom flutter in VCR mode, the frequency of the clock can be ’hold’ by
’freezing’ the increment of the HPLL. The vertical-frequency ’freezing-time’ starts a
number of lines (programmable by the
for a number (programmable) of lines. The settings do not depend on
functionality is only available for the 1fh mode (2FH = 0).
Figure 17
I
can be Frozen
An active low reset signal for other chips is available at pin RESOUTN. It is activated
when the chip supply voltage
RESOUTN also is activated by pin RESIN. The RESOUTN pulse signal is not cancelled
until the crystal oscillator resonates and in addition stretched by an internal circuit for
approximately 127 lines (8 ms).
2
C-Bus Programming Area which Clock Frequency Value Generated by HPLL
VS
Line Number
of Half Picture
Range over which
Frequency Value
is Frozen
(In this example the frequency value was frozen 13 lines before the VS pulse and for
a duration of 11 lines.)
15
14
Start 0...15 Lines before VS
Start
13
0
V
DD
12
1
is switched on or when voltage glitches occur on it.
10
3
I
2
n-2
C Bus) before the vertical pulse and then lasts
Stop
26
11
2
n-1
0...15 Lines Duration
12
1
n
13
0
n = Number of Lines
1
14
in preceding Half Picture
2
15
3
4
UED10466
I
2
C-Bit TV. This
5
SDA 9206
1999-02-10