SDA9257 Infineon Technologies Corporation, SDA9257 Datasheet - Page 33

• Manufacturer Part Number: SDA9257
• Description: Clock SYNC Generator
• Manufacturer: Infineon Technologies Corporation

Subaddress 06
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Semiconductor Group
Name
TV
FREE
VOFF
VF
TERM
GENMOD Clock generator mode
0
SYPOL
H
Function
Selection of HPLL lock-in behavior:
0:
1:
Generation of V pulse:
0:
1:
Vertical noise suppression:
0:
1:
Number of lines per field:
0:
1:
Note: VF must be set to the number of lines present in SYNC for
Terminal mode:
FREE
don’t care 1
don’t care 1
1
1
1
1
0:
1:
Reserved
SYNC polarity:
0:
1:
fly-wheel and noise suppression modes. VF determines
the number of lines per field for the free-running or
terminal mode.
Optimum for VCR
Optimum for SYNC from network
V derived from SYNC
Free-running generation; vertical frequency is
determined by VF bit, VOFF bit is enabled, SCHW bit
should be set to 1
Noise suppression enabled
No noise suppression
312.5 or 312
262.5 or 262
Normal PLL mode
Generator mode (fixed frequency output,
controlled by INC)
Negative sync signals (normal SYNC input)
Positive sync signals
TERM
0
0
0
0
33
SCHW
don’t care 0
don’t care 1
1
1
0
0
VF
0
1
0
1
Number of Lines
per Field generated
in Free-Running Mode
312
262
312.5
262.5
339
279
SDA 9206
1999-02-10