T15V8M16A TM tech, T15V8M16A Datasheet - Page 7

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T15V8M16A

Manufacturer Part Number
T15V8M16A
Description
512K X 16 LOW POWER CMOS STATIC RAM
Manufacturer
TM tech
Datasheet
(Address Controlled,
tm
TIMING WAVEFORMS
READ CYCLE 1
READ CYCLE 2 (
(Chip Enable Controlled)
Notes (READ CYCLE) :
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
4. At any given temperature and voltage condition. t
5. Transition is measured 200mV from steady state voltage with load.
6. Device is continuously selected with
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
V
and from device to device interconnection.
100% tested.
HZ
Ad dr es s
A d d r e s s
U B
OH
and t
D OUT
D
or V
/ L B
C E
OUT
O E
OHZ
OL
CH
TE
levels.
Previous Data Valid
are defined as the time at which the outputs achieve the open circuit condition referenced to
CE
High-Z
WE
=
t OH
=
OE
V
IH
)
t
LZ
=
t AA
t
B LZ
V ,
IL
CE
t
OLZ
t
t
t
A C E
B A
A A
WE
=V
t
OE
IL
=
.
V
IH
HZ
t RC
(max.) is less than t
,
t
R C
LB
P. 7
or/and
Data Valid
Preliminary T15V8M16A
UB
=
This parameter is sampled and not
LZ
V )
(min.) both for a given device
IL
Publication Date: JAN. 2000
t
OH Z
t
B H Z
t
HZ
t
OH
DON'T CARE
UNDEFINED
Revision:0.A

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