MT28C3224P20 Micron Technology, MT28C3224P20 Datasheet - Page 17
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MT28C3224P20
Manufacturer Part Number
MT28C3224P20
Description
FLASH AND SRAM COMBO MEMORY
Manufacturer
Micron Technology
Datasheet
1.MT28C3224P20.pdf
(42 pages)
NOTE: 1. Full status register check can be done after each word or after a sequence of words.
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
FULL STATUS REGISTER CHECK FLOW
Automated Word Programming
Issue PROGRAM SETUP
Word Program Passed
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation
Read Status Register
Read Status Register
Issue Word Address
Full Status Register
Check (optional)
attempts.
and Word Data
Command and
Word Program
Word Address
Completed
SR7 = 1?
SR1 = 0?
SR3 = 0?
SR4 = 0?
Start
Bits
Bits
YES
YES
YES
YES
Flowchart
1
Figure 4
NO
NO
NO
NO
PROGRAM Attempted
Word Program Failed
on a Locked Block
V
PP
PROGRAM
SUSPEND?
NO
Range Error
SUSPEND Loop
PROGRAM
YES
17
256K x 16 SRAM COMBO MEMORY
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
READ
Standby
Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby
Standby
Standby
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16 PAGE FLASH
WRITE
PROGRAM
SETUP
WRITE
DATA
Data =
Addr =
Data =
Addr =
Status register data;
toggle OE# or CE# to update
status register.
Check SR7
1 = Ready, 0 = Busy
1 = Detect locked block
1 = Detect V
1 = Word program error
Check SR1
Check SR3
Check SR4
40h or 10h
Address of word to be
programmed
Word to be
programmed
Address of word to be
programmed
2
3
PP
©2002, Micron Technology, Inc.
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