MT9173AE Mitel Networks Corporation, MT9173AE Datasheet

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... CDSTo/ Interface CDo RxSB 2 ISO -CMOS ST-BUS Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB MT9173AE MT9173AN MT9173AP MT9174AE MT9174AN MT9174AP Description The MT9173 (DSIC) and MT9174 (DNIC) are functionally identical to the MT9171/72 except for the addition of one feature. The MT9173/74 include a digital output pin indicating the temporal position of the received " ...

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MT9173/ LOUT 2 23 VBias 22 3 VRef 21 MS2 MS1 19 MS0 6 18 RegC 7 RxSB F0/CLD 15 10 CDSTi/CDi 14 11 CDSTo/CDo 13 12 VSS 24 PIN PDIP/ ...

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Preliminary Information Pin Description (continued) Pin # Name F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital mode a 244 ns wide negative pulse indicating the end of the active channel times of the ...

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MT9173/ DSTi DSTo F0o Channel Time 0 Figure Port - 80 kbit/s (Modes DSTi ...

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Preliminary Information Functional Description The MT9173 and MT9174 are multifunction devices capable of providing high speed, full duplex digital transmission 160 kbit/s over a twisted wire pair. They use adaptive echo-cancelling techniques and transfer data in a ...

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MT9173/74 9-142 Preliminary Information ...

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Preliminary Information In DIGITAL NETWORK (DN) mode, upon entering the DNIC from the DV and CD ports, the B-channel data, D-channel D0 (and D1 for 160 kbit/s), the HK bit of the C-channel (160kbit/s only) and a SYNC bit are ...

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MT9173/74 of the near end signal may be disabled by holding the Precan pin high. This mode simplifies the design of external line transceivers used for loop extension applications. The Precan pin features an internal pull-down which allows this unconnected ...

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Preliminary Information select the DNIC to operate as a MASTER or SLAVE, in DUAL or SINGLE port operation, in MODEM or DIGITAL NETWORK mode and the order of the C and D channels on the CD port. Table 2 provides ...

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MT9173/74 determine which of the DNICs is using the externally supplied clock and which is phase locking to the data on the line. Due to jitter and end to end delay, one end must be the master to generate all ...

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Preliminary Information receiving signalling information and lower speed data between the line and the system. In DN/DUAL mode the DNIC receives a C-channel on CDSTi while transmitting a C-channel on CDSTo. channel times later (halfway through the frame ...

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MT9173/74 C-Channel Internal Control (Bit 0-7) Register XXX01111 00000000 XXX11111 00010000 Notes: Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode. Default Mode 2 can also be selected by tying ...

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Preliminary Information 0 1 SYNC CHQual Status Name Register 0 SYNC Synchronization - When set this bit indicates that synchronization to the received line data sync pattern has been acquired. For DN mode only. 1-2 CHQual Channel Quality - These ...

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MT9173/74 Bits Bit 7 Bit 6 Data 1 1 NRZ Data Differential Encoded Differential Encoded Biphase Transmit Line Signal Note: Last bit sent was a logic SYNC OUT Figure 11 - Frame Format ...

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Preliminary Information Applications Typical connection diagrams are shown in Figures 13 and 14 for the DN mode as a MASTER and SLAVE, respectively connected to the coupling OUT transformer through a resistor R2 and capacitors C2 and C2’ ...

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MT9173/74 Absolute Maximum Ratings Parameter 1 Supply Voltage 2 Voltage on any pin (other than supply) 3 Current on any pin (other than supply) 4 Storage Temperature 5 Package Power Dissipation (Derate 16mW/ C above Exceeding these ...

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Preliminary Information AC Electrical Characteristics Characteristics 1 Input Voltage 2 Input Impedance I 3 Crystal/Clock Frequency Crystal/Clock Tolerance U 5a Crystal/Clock Duty Cycle Crystal/Clock Duty Cycle 6 Crystal/Clock Loading 7 Output Capacitance O U ...

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MT9173/74 2.0V C4 0.8V 2.0V F0 0.8V Figure Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode 2.0V C4 0.8V 3.0V OSC1 2.0V Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in ...

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Preliminary Information AC Electrical Characteristics Characteristics 1 DSTi/CDSTi Data Setup Time 2 DSTi/CDSTi Data Hold Time 3a DSTo/CDSTo Data Delay 3b DSTo/CDSTo High Z to Data Delay † Timing is over recommended temperature & power supply voltage ranges. * Typical ...

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MT9173/74 Tx Bit Stream 2.4V TCK 0.4V 2.0V Di CDI 0.8V 2.4V CDo 0.4V Rx Bit Stream RCK 2.4V Do 0.4V Figure 20 - Data Timing for Master Modem Mode 9-156 Bit Cell Bit Cell t ...

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Preliminary Information 2.4V TCK 0.4V 2.0V Di CDI 0.8V 2.4V CDo 0.4V RCK 2.4V Do 0.4V Figure 21 - Data Timing for Slave Modem Mode F0 RxSB AC Electrical Characteristics Characteristics 1 RxSB Delay * Typical figures are at 25 ...

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MT9173/74 Notes: 9-158 Preliminary Information ...