MT9173AE Mitel Networks Corporation, MT9173AE Datasheet - Page 8

• Manufacturer Part Number: MT9173AE
• Description: Digital Subscriber Interface Circuit with RxSB
• Manufacturer: Mitel Networks Corporation

MT9173/74
of the near end signal may be disabled by holding
the Precan pin high. This mode simplifies the design
of external line transceivers used for loop extension
applications.
pull-down
unconnected in applications where this function is
not required. The resultant signal passes through
a receive filter to bandlimit and equalize it. At this
point, the echo estimate from the echo canceller is
subtracted from the precancelled received signal.
This difference signal is then input to the echo
canceller as an error signal and also squared up by a
comparator and passed to the biphase receiver.
Within the echo canceller, the sign of this error signal
is determined.
estimate is either incremented or decremented and
this new estimate is stored back in RAM.
The timebase in both SLV and MAS modes
(generated internally in SLV mode and externally in
MAS mode) is phase-locked to the received data
stream.
Biphase Decoder, Descrambler and Deprescrambler
in MAS mode and the entire chip in SLV mode. The
Biphase Decoder decodes the received encoded bit
stream resulting in the original NRZ data which is
passed onto the Descrambler and Deprescrambler
where the data is restored to its original content by
performing the reverse polynomials. The SYNC bits
are extracted and the Receive Interface separates
the channels and outputs them to the proper ports in
the proper channel times.
various channels is the same as that received on the
input DV and CD ports.
The Transmit/Receive Timing and Control block
generates all the clocks for the transmit and receive
functions and controls the entire chip according to
the control register.
DNIC may be connected to the same DV and
CD ports an F0o signal is generated which signals
the next device in a daisy chain that its channel times
are now active.
E=Enabled
Blanks are disabled
9-144
MS2
Mode Select Pins
0
0
0
0
1
1
1
1
MS1
0
0
1
1
0
0
1
1
This phase-locked clock operates the
which
X=Not Applicable
The Precan pin features an internal
Depending on the sign, the echo
MS0
In this arrangement only the first
0
1
0
1
0
1
0
1
allows
In order that more than one
Mode
0
1
2
3
4
5
6
7
this
The destination of the
pin
SLV
E
E
E
to
MAS
Table 1. Mode Select Pins
be
E
E
E
E
E
left
DUAL
E
E
E
E
E
E
DNIC in the chain
the following devices receiving its predecessor’s F0o.
In MOD mode, all the ports have a different format.
The line port again operates at 80 or 160 kbit/s,
however, there is no synchronization overhead, only
transparent data. The DV and CD ports carry serial
data at 80 or 160 kbit/s with the DV port transferring
all the data for the line and the CD port carrying the
C-channel only. In this mode the transfer of data at
both ports is synchronized to the TCK and RCK
clocks for transmit and receive data, respectively.
The CLD signal goes low to indicate the start of the
C-channel data on the CD port. It is used to load
and latch the input and output C-channel but has no
relationship to the data on the DV port.
In DN MAS mode, the RxSB pin outputs a pulse
corresponding to the position of the synchronization
bit within the received biphase data stream. Since
the delay in transmission between DNICs is
dependent upon line length, the position of the RxSB
pulse will vary as the line length is varied. This
feature can be used to determine total loop delay
which is necessary in wireless base stations where
all of the microcells need to be synchronized. In DN
SLV mode, The RxSB pin is also active although its
timing is fixed and does not vary with line length. For
both DN MAS and SLV modes, the RxSB pin can be
also used as a hardware SYNC indicator. In MODEM
mode, for both MAS and SLV ends, the RxSB pin is
inactive and held low.
Operating Modes (MS0-2)
The logic levels present on the mode select pins
MS0, MS1 and MS2 program the DNIC for different
operating modes and configure the DV and CD ports
accordingly.
corresponding to the state of MS0-2. These pins
SINGL
Operating Mode
E
E
MOD
E
E
Table
Preliminary Information
DN
E
E
E
E
E
E
receives the system F0 with
1
D-C
shows
E
X
E
E
X
E
C-D
X
E
X
E
the
modes
ODE
E
E
E
E
E
E
E