MT9V403 Micron, MT9V403 Datasheet
MT9V403
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MT9V403 Summary of contents
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... Exposure trigger (snapshot mode), exposure and readout timing (slave mode) • Color Specifications: monochrome or color (Bayer pattern) 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR MT9V403 ...
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... VLNS Input 17 VLN1 Input 19 VLP Input 13 VOFF Input 16 V Input REF 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Figure 1: Block Diagram Expose Sensor Row Row Control Pixel Array Interface Decoder Logic Block System Clock Gain Control ...
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... D Power GND 35, 44 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR DESCRIPTIONS ADC reference voltage that sets the maximum input signal level, setting the size of the least significant bit (LSB) in the analog to digital conversion process. ...
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... MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR signals utilized in master mode are depicted in Figure 4. In master mode, the start of the integration period is determined internal to the MT9V403. Figure 4: Master Mode Interface (502, 667) 8 494 CONTROLLER The integration time is pre-programmed via the two-wire serial interface and indicated by the EXPOSE signal going HIGH ...
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... HB is the horizontal blanking in SYSCLK cycles (255 clock maximum) specified in register 5. When vertical blanking is utilized, the FRAME_ VALID signal stays LOW for an additional user pro- 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 652 653 ...
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... DATA [9:0] XXX (output) NOTE: Vertical blanking is nominally 1 SYSCLK and 0 row times, and may be increased by using register 6. 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR EXPOSURE TIME > READOUT TIME Frame Time = Exposure Time Frame Time = Exposure Time + VB shown in Figure 6 and Figure 7 ...
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... Figure 9. In snapshot mode the start of the integration period is determined by the externally applied EXPOSE pulse that the user inputs to the MT9V403. The integration time is prepro- grammed via the two-wire interface. After each frame's integration period is complete, the readout process commences and the FRAME_VALID, ROW_ VALID, and DATA signals are output ...
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... The dura- tion of the ROW_STRT signal should be one clock cycle. 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR The column counter selects the column output SRAM cells for off-chip readout at the speed of SYSCLK ...
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... The method of operation selected is determined by the means in which the user supplies the control signals. In simultaneous slave mode the exposure period occurs during readout. The row and frame synchroni- 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR TX_N PG_N ...
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... RESMEM (input) TX_N (input) FRAME_SYNC_N (input) ROW_STRT (input) LD_SHFT_N (input) DATA [9:0] Row Row Row 502 1 2 (output) 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Settings) >100 <600 ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ...
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... Minimum Duration (input) 338 SYSCLK TX_N (input) FRAME_SYNC_N (input) ROW_STRT (input) LD_SHFT_N (input) DATA [9:0] Row Row 502 1 (output) 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR waveforms are shown in Figures 15 and 16, respec- tively >10 SYSCLK ) ) ) ) XXX ) ( ( ...
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... Figure 17: Extended High Dynamic Range Timing in Slave Mode TX_N PG_N DATA [9:0] Figure 18: Output Signal vs. Photocurrent 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR N2. For N1 = 500 and the dynamic range enhancement is approximately 48 dB. Figure 18 shows output signal vs. photocurrent. The knee point is dependent on the VRSTLOW bias, which determines the charge capacity of the photodiode ...
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... The MT9V403 uses a 16-bit data for its internal registers, thus requiring two eight-bit transfers to write to one register. To write/read this 16-bit data, first per- form a write/read the eight MSBs, then perform another write/read for eight LSBs ...
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... SDATA B8b ADDR START ACK 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR sor will give an acknowledge bit. All 16 bits must be written before the register will be updated. After 16 bits are transferred, the register address should be incre- mented, so that the next 16 bits are written to the next register ...
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... Bit disable internal bias. Bit high bias. Bit low bias. Bits 3–6, 8–15 not used, set to 0. 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR FUNCTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Gain settings range is from 1 (00000001 (00010010). W/R Reg53 Global gain control. Bit gain is multiplied by factor of 0.5 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR FUNCTION Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 REGISTER ...
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... Reg143 ADC calibration data output register. Register Start-up Sequence Upon powering up the MT9V403, the sensor should be reset by bringing the LRST_N pin LOW. This will ini- tialize all of the registers to their default values. Upon the release of reset, the sensor will perform ADC cali- bration ...
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... Decreasing the number of columns has no effect on frame rate. For example, for the full 667 col- umn by 502 row resolution the MT9V403 operates at 196 fps, but if the vertical resolution is decreased by half (i.e., 251 rows) the frame rate increases propor- tionally so the frame rate is doubled to 392 fps ...
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... Start Row 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR delay. Even though the windowed columns can be readout at the beginning of a row, the user must still wait the required 671 clock cycles for the row process- ing to complete before initiating the processing of the next row with ROW_STRT ...
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... For the master and snapshot mode the electronic shutter's exposure duration (integration time) is pro- grammed via the two-wire serial interface. The MT9V403 shutter can be operated to generate continu- ous video output (simultaneous master mode or sequential master mode) or capture single images (snapshot mode). ...
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... VLN_AMP: Internal default value is recommended. V REF ADC Calibration The MT9V403 contains a special self-calibrating cir- cuitry that enables it to reduce its own column-wise fixed-pattern noise. This calibration process consists of connecting a calibration signal to each of the 167 ADC inputs and estimating and storing these 167 off- sets (as 7 bits) to subtract from subsequent samples ...
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... Calibration will continue to occur every frame until a zero is written to register 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR REGISTER 53 0 ...
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... GLOBAL LOGIC RESET FRAME_VALID ROW_VALID The calibration coefficients can be read from the MT9V403 and written to it, making it possible to fur- ther reduce column-wise fixed pattern noise by exter- nally calculating and writing the proper offset values to the MT9V403. For example, the user may choose to ...
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... All bias pins should be decoupled with 0.1µF ceramic and 10µF electrolytic capacitors. (Please see board connections.) Capacitors should be placed as physically close as possible to the MT9V403 package. 3. Digital outputs can drive standard CMOS circuits with 30pF load, but less load capacitance results in less substrate noise on-chip ...
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... Figure 30: Propagation Delays for Data Output, Frame Valid, and Row Valid Signals FRAME_VALID ROW_VALID 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Tplh Tphl D, D SYSCLK DOUT(9:0) tr Tplh F SYSCLK FRAME_VALID tr Tplh L SYSCLK ROW_VALID tr 25 Tphl F SYSCLK ...
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... This device contains circuitry to protect the inputs against damage from high static voltages or electric fields, but the user is advised to take precautions to avoid the application of any voltage higher than the maximum rated. 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR ...
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... SCLK SDATA NOTE: All timing are in units of master clock cycle. 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR transitions. These are specified below in master clock cycles. Figure 33: Serial Host Interface Data Timing for Write SDATA NOTE: SDATA is driven by an off-chip transmitter ...
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... After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used. 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 6 ...
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... Pixel Size X-Y dimensions Pixel Pitch Center-to-center pixel spacing Pixel Fill Factor Area of drawn active area Shutter Efficiency Equals: 1-(leakage into in pixel memory) 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR PARAMETER 1 = 1V) REF PARAMETER 29 TYP 1,800 0 ...
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... Figure 38: Quantum Efficiency – Color 350 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 450 550 650 750 Wavelength (nm) 450 550 650 750 Wavelength (nm) Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Tolerance on die placement is ±0.25mm. 3. Rotation <2°. 4. Tilt ±2 mils. Figure 40: Package Drawing – Top View NOTE: 1. Dimensions in mm. MAX 2. ------------- - MIN 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 14.22±.013 (Square) 9.149 (502, 667) 4.97 1.318±0.2 6.61 (1, 1) PIN 1 0.267± ...
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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and TrueSNAP are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 11.18 TYP 1 ...
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... IN • Added high-static note to DC Characteristics Table Rev 0.7, Preliminary ........................................................................................................................................................8/03 • Initial Release of document 09005aef80c07280 MT9V403_DS.fm - Rev. B 1/04 EN 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 ©2004 Micron Technology. Inc. ...