MT9V403 Micron, MT9V403 Datasheet - Page 4

• Manufacturer Part Number: MT9V403
• Description: 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
• Manufacturer: Micron

Pixel Data Format
below.
Output Format and Timing
master, snapshot, or slave mode. Additionally, master
mode can be setup to allow simultaneous integration
and readout (simultaneous master mode) or sequen-
tial integration and readout (sequential master mode).
Mode selection is done via the two-wire serial inter-
face, taking less than one frame time to switch
between modes.
read out the visible pixels. Therefore, the start row is 1,
start column is 9, end row is 480 and the end column is
648.
Master Mode
timing to initiate exposure and readout. The interface
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
The pixel array descriptions and details are shown
The sensor can operate in three interface modes:
The default register settings program the imager to
In master mode the sensor internally generates the
Figure 3: Pixel Color Pattern Detail
Figure 2: Pixel Array Description
Dark and Isolation
Pixels
black pixels
(Bottom Left Corner)
(1, 1)
8
G
G
G
G
B
B
B
Active Pixel Array
G
G
G
R
R
R
R
G
G
G
G
B
B
B
659
G
G
G
R
R
R
R
G
G
G
G
B
B
B
(502, 667)
G
G
G
R
R
R
R
G
B
G
B
G
B
G
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
494
8
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
4
signals utilized in master mode are depicted in
Figure 4. In master mode, the start of the integration
period is determined internal to the MT9V403.
two-wire serial interface and indicated by the EXPOSE
signal going HIGH. When the sensor commences, the
readout process the FRAME_VALID, ROW_VALID, and
DATA signals are output, as shown in Figure 5 on
page 5.
relationships are as shown in Figure 5 on page 5. The
FRAME_VALID signal goes HIGH, indicating the start
of frame, and 2.5 clock cycles later the ROW_VALID
signal goes HIGH, indicating the start of the first row.
The first data bit is valid on the first falling edge of
SYSCLK after ROW_VALID goes HIGH. The remaining
665 pixels for the row are valid on the subsequent fall-
ing edges of SYSCLK, after which ROW_VALID returns
to the LOW state. (Please note that in master mode 648
pixels are readout for each row.) The ROW_VALID will
then be an active HIGH envelope for subsequent rows
and the FRAME_VALID signal will be an active HIGH
envelope for subsequent frames. The time required for
one complete row operation is 671 clock cycles: 1 clock
cycle delay + 666 columns + 4 clock cycles when
ROW_VALID is LOW. With a SYSCLK of 66 MHz, this
translates into a row time of 10.2µs and a frame time of
5.1ms for full resolution (502 rows). This assumes there
is no vertical blanking or horizontal blanking and that
the exposure time is less than 5.1ms. If exposure time
becomes greater than 5.1ms, the frame time then
becomes the inverse of the exposure time (1/[exposure
time]).
The integration time is pre-programmed via the
The master mode row synchronization waveform
CONTROLLER
Figure 4: Master Mode Interface
Micron Technology, Inc., reserves the right to change products or specifications without notice.
FRAME_VALID
Signals
ROW_VALID
EXPOSE
SYSCLK
LRST_N
DATA
©2004 Micron Technology. Inc.
MT9V4O3