PM7312 pmc-sierra, PM7312 Datasheet - Page 141

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
FLAG[2:0]
LEVEL[3:0]
IDLE
The flag insertion control (FLAG[2:0]) configures the minimum number of flags or bytes of
idle bits the HDLC processor inserts between HDLC packets. The value of FLAG[2:0] to be
written to the channel provision RAM, in an indirect channel write operation, must be set up in
this register before triggering the write. The minimum number of flags or bytes of idle (8 bits
of 1’s) inserted between HDLC packets is shown in the table below. FLAG[2:0] reflects the
value written until the completion of a subsequent indirect channel read operation.
Table 18 FLAG[2:0] Settings
The indirect channel FIFO trigger level (LEVEL[3:0]), in concert with the TRANS bit,
configure the various channel FIFO free space levels which trigger the HDLC processor to start
transmission of a HDLC packet as well as trigger the partial packet buffer to request data from
the upstream device as shown in the following table. The channel FIFO trigger level to be
written to the channel provision RAM, in an indirect write operation, must be set up in this
register before triggering the write. LEVEL[3:0] reflects the value written until the completion
of a subsequent indirect channel read operation.
The HDLC processor starts transmitting a packet when the channel FIFO free space is less than
or equal to the level specified in the appropriate Start Transmission Level column of the
following table or when an end of a packet is stored in the channel FIFO. When the channel
FIFO free space is greater than or equal to the level specified in the Starving Trigger Level
column of the following table and the HDLC processor is transmitting a packet and an end of a
packet is not stored in the channel FIFO, the partial packet buffer makes expedited requests to
the upstream device to retrieve XFER[3:0] + 1 blocks of data.
The inter-frame time fill bit (IDLE) configures the HDLC processor to use flag bytes or HDLC
idle as the inter-frame time fill between HDLC packets. The value of IDLE to be written to the
channel provision RAM, in an indirect channel write operation, must be set up in this register
before triggering the write. When IDLE is set low, the HDLC processor uses flag bytes as the
inter-frame time fill. When IDLE is set high, the HDLC processor uses HDLC idle (all one’s
bit with no bit-stuffing pattern is transmitted) as the inter-frame time fill. IDLE reflects the
value written until the completion of a subsequent indirect channel read operation.
FLAG[2:0]
000
001
010
011
100
101
110
111
Minimum Number of Flag/Idle Bytes
1 flag / 0 Idle byte
2 flags / 0 idle byte
4 flags / 2 idle bytes
8 flags / 6 idle bytes
16 flags / 14 idle bytes
32 flags / 30 idle bytes
64 flags / 62 idle bytes
128 flags / 126 idle bytes
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
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