PM7312 pmc-sierra, PM7312 Datasheet - Page 264

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
14.10 Microprocessor Interface
Figure 54 Read Followed by Write Timing for ZBT Mode
Figure 55 Read Followed by Write Timing for Standard SSRAM Mode
The following diagrams illustrate the various handshaking required for microprocessor reads and
writes.
Figure 56 shows a single read and write operation to the non-burstable register space with bus
polarity set to 1. On the first cycle, BURSTB is sampled inactive; therefore, it is expected that the
cycle is a single data transfer, and the BLAST signal is of no significance. The subsequent 2 cycles
have BURSTB sampled active hence the transfer cycle is terminated when both BLAST and
READYB are asserted. Note that between each transfer, there is a turn around cycle provided by
the external interface to ensure that there is no bus contention on back to back transfers on the AD
bus.
CC_RDDATA [35:0]
CC_RDDATA [35:0]
CC_WRDATA[35:0]
CC_WRDATA[35:0]
CC_ADDR[17:0]
CC_ADDR[17:0]
CC_SELB
CC_SELB
CC_WEB
CC_WEB
SYSCLK
SYSCLK
R0
R0
1
1
R1
2
R1
2
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Q0
3
Q0
3
Q1
4
W0
Q1
4
5
W1
5
W0
D0
6
D0
6
W1
D1
7
R2
R2
D1
8
7
9
8
10
Q2
Q2
9
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