SST49LF016C SST, SST49LF016C Datasheet - Page 12

• Manufacturer Part Number: SST49LF016C
• Description: 16 Mbit LPC Serial Flash
• Manufacturer: SST

Data Sheet
FIRMWARE MEMORY CYCLES
Firmware Memory Read Cycle
TABLE 4: Firmware Memory Read Cycle Field Definitions
©2006 Silicon Storage Technology, Inc.
FIGURE 5: Firmware Memory Read Cycle Waveform
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
(A+1)
(A+2)
14-A
3-9
10
11
12
13
LFRAME#
1
2
LAD[3:0]
LCLK
MADDR
RSYNC
START
MSIZE
IDSEL
Name
TAR0
TAR1
TAR0
TAR1
Field
DATA
1101b 0000b
Start
IDSEL
Field Contents
A[27:24]
0000 (READY)
0000 to 1111
1111 (float)
1111 (float)
LAD[3:0]
YYYY
KKKK
ZZZZ
A[23:20] A[19:16]
1101
1111
1111
1
MADDR
A[15:12]
A[11:8]
then Float
then Float
Direction
then OUT
LAD[3:0]
then IN
Float,
Float,
OUT,
OUT
OUT
IN,
IN
IN
IN
IN
A[7:4]
A[3:0]
12
The MSIZE field indicates how many bytes will be trans-
MSIZE
Comments
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions high)
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
Indicates which SST49LF016C device should respond.
If the IDSEL (ID select) field matches the value of ID[3:0],
then that particular device will respond to the LPC bus
cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
ferred during multi-byte operations.
Device will execute multi-byte read of 2
SST49LF016C supports only MSIZE = 0, 1, 2, 4, 7 (1, 2, 4,
16, 128 Bytes), with KKKK=0000b, 0001b, 0010b, 0100b, or
0111b.
In this clock cycle, the master has driven the bus to all ‘1’s
and then floats the bus, prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
The SST49LF016C takes control of the bus during this
cycle.
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data. The least-significant nibble of the least-significant byte
will be available during the next clock cycle.
A=(13+2
Least significant nibbles outputs first.
In this clock cycle, the SST49LF016C drives the bus to all
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
A=(13+2
The host resumes control of the bus during this cycle.
A=(13+2
KKKKb
TAR0
1111b
n+1
n+1
n+1
Tri-State
TAR1
); n = MSIZE
); n = MSIZE
); n = MSIZE
RSYNC
0000b
D
0
16 Mbit LPC Serial Flash
[3:0]
D
0
[7:4]
DATA
D
n
[3:0]
SST49LF016C
MSIZE
D
S71237-07-000
n
[7:4]
1237 F03.0
bytes.
TAR
T4.0 1237
9/06