SST49LF016C SST, SST49LF016C Datasheet - Page 25

• Manufacturer Part Number: SST49LF016C
• Description: 16 Mbit LPC Serial Flash
• Manufacturer: SST

16 Mbit LPC Serial Flash
SST49LF016C
AAI Data Load Protocol
TABLE 19: AAI Programming Cycle (initiated with WP#/AAI at V
©2006 Silicon Storage Technology, Inc.
Clock Cycle
1
2
3-9
10
11-266
FIGURE 8: AAI Load Protocol Waveform
(Data Strobe Input)
LFRAME#
WP#/AAI
LAD[3:0]
RY/BY#
Field Name
START
IDSEL
MADDR
MSIZE
DATA
LCLK
LD#
V
H
Start
1 2 3 4 5 6 7 8 9 10 11 12
IDSEL
Field Contents
1110
0000b to 1111b
YYYY
KKKK
ZZZZ
Address
MADDR
MSIZE
LAD[3:0]
IN
IN
IN
IN
IN
Byte 0
DATA
25
DATA
Byte N
Comments
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized. The START field contents
indicate a Firmware Memory Write cycle. (1110b)
ID works identically to Firmware Memory cycle.
This field indicates which SST49LF016C device
should respond. If the IDSEL (ID select) field matches
the value of ID[3:0], then that particular device will
respond to the whole bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
Only bits [20:7] of the total address [27:0] are used for
AAI mode. The rest are “don’t care”.
MSIZE field is don’t care when in AAI mode
Data is transmitted to the device least significant nib-
ble first, from byte 0 to byte 127 as long as the RY/BY#
is high and LD# low. The host will pause the clock and
data stream when RY/BY# goes low until it returns
high, signifying that the chip is ready for more data
DATA
Byte
N+1
H
ONLY)
DATA
Byte
2N
DATA DATA
Byte
126
264
Byte
127
266
S71237-07-000
1237 F08.1
Data Sheet
T19.0 1237
9/06