SST49LF016C SST, SST49LF016C Datasheet - Page 9

• Manufacturer Part Number: SST49LF016C
• Description: 16 Mbit LPC Serial Flash
• Manufacturer: SST

16 Mbit LPC Serial Flash
SST49LF016C
PIN DESCRIPTIONS
TABLE 1: Pin Description
©2006 Silicon Storage Technology, Inc.
Symbol
LCLK
LAD[3:0]
LFRAME# Frame
RST#
INIT#
ID[3:0]
GPI[4:0]
TBL#
WP#/AAI
WP#/AAI
RY/BY#
LD#
V
V
NC
DD
SS
1. I=Input, O=Output
General
Ready/Busy#
Pin Name
Clock
Address
and Data
Reset
Initialize
Identification
Inputs
Purpose
Inputs
Top Block Lock
Write Protect
AAI Enable
Load-Enable#
Power Supply
Ground
No Connection
Type
PWR
PWR
I/O
O
I
I
I
I
I
I
I
I
I
I
1
AAI LPC
N/A
Interface
X
X
X
X
X
X
X
X
X
X
X
N/A
X
X
X
X
X
X
X
X
X
X
X
Functions
To accept a clock input from the control unit
To provide LPC bus information, such as addresses and command Inputs/
Outputs data.
To indicate the start of a data transfer operation;
also used to abort an LPC cycle in progress.
To reset the operation of the device
This is the second reset pin for in-system use.
This pin is internally combined with the RST# pin.
If this pin or RST# pin is driven low, identical operation is exhibited.
These four pins are part of the mechanism that allows multiple parts to be
attached to the same bus. The strapping of these pins is used to identify
the component. The boot device must have ID[3:0]=0000, all subsequent
devices should use sequential up-count strapping. These pins are inter-
nally pulled-down with a resistor between 20-100 KΩ. When in AAI mode,
these pins operate identically as in Firmware Memory cycles.
These individual inputs can be used for additional board flexibility.
The state of these pins can be read through LPC registers. These inputs
should be at their desired state before the start of the LPC clock cycle dur-
ing which the read is attempted, and should remain in place until the end
of the Read cycle. Unused GPI pins must not be floated.
GPI[2:4] are ignored when in AAI mode.
When low, prevents programming to the boot block sectors at top of device
memory. When TBL# is high it disables hardware write protection for the
top block sectors. This pin cannot be left unconnected.
TBL# setting is ignored when in AAI mode.
When low, prevents programming to all but the highest addressable block
(Boot Block). When WP# is high it disables hardware write protection for
these blocks. This pin cannot be left unconnected.
When set to the Supervoltage V
multiple bytes in AAI mode. When brought to V
LPC mode.
Open drain output that indicates the device is ready to accept data in an
AAI mode, or that the internal cycle is complete.
Used in conjunction with LD# pin to switch between these two flag states.
Input pin which when low, indicates the host is loading data in an AAI pro-
gramming cycle. If LD# is high, the host signals the AAI interface that it is
terminating a command. LD# low/high switches the RY/BY# output from a
“buffer free” flag to a “programming complete” flag.
To provide power supply (3.0-3.6V)
Circuit ground (0V reference)
Unconnected pins.
9
H
= 9V, configures the device to program
IL
/V
IH
, returns device to
S71237-07-000
Data Sheet
T1.2 1237
9/06