ISL6208 Intersil Corporation, ISL6208 Datasheet - Page 7

• Manufacturer Part Number: ISL6208
• Description: High Voltage Synchronous Rectified Buck MOSFET Driver
• Manufacturer: Intersil Corporation

Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6208 will detect the zero current crossing of the output
inductor and turn off LGATE. This ensures that
discontinuous conduction mode (DCM) is achieved. Diode
emulation is asynchronous to the PWM signal. Therefore,
the ISL6208 will respond to the FCCM input immediately
after it changes state. Refer to the waveforms on page 6.
NOTE: Intersil does not recommend Diode Emulation use with
r
MOSFET can cause gross current measurement inaccuracies.
Three-State PWM Input
A unique feature of the ISL6208 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from the following equation:
where Q
charge the gate of the upper MOSFET. The ΔV
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125μF is required.
The next larger standard value capacitance is 0.15μF. A
good quality ceramic capacitor is recommended.
C
DS(ON)
BOOT
current sensing topologies. The turn-OFF of the low side
≥
GATE
----------------------- -
ΔV
GATE
Q
GATE
BOOT
is the amount of gate charge required to fully
, of 25nC at 5V and also assume the droop in
7
BOOT
term is
(EQ. 1)
ISL6208
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of +125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
where f
and V
and Q
MOSFET selection and any external capacitance added to
the gate pins. The lV
of the driver and is typically negligible.
P
=
FIGURE 8. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
1000
f
900
800
700
600
500
400
300
200
100
sw
L
L
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
FIGURE 9. POWER DISSIPATION vs FREQUENCY
0
sw
represent the upper and lower gate rail voltage. Q
(
is the upper and lower gate charge determined by
0
0.0
1.5V
Q
Q
20nC
is the switching frequency of the PWM signal. V
U
L
200
= 200nC
U
0.1
=100nC
VOLTAGE
Q
U
400
+
0.2
Q
V
GATE
CC
L
600
Q
0.3
Q
L
V
Q
= 100nC
L
)
FREQUENCY (kHz)
U
CC
+
= 100nC
ΔV
800 1000 1200 1400 1600 1800 2000
= 50nC
I
0.4
VCC
BOOT_CAP
product is the quiescent power
V
0.5
CC
0.6
(V)
0.7
0.8
Q
Q
Q
Q
U
L
U
L
March 30, 2007
= 50nC
= 50nC
=50nC
= 20nC
0.9
(EQ. 2)
FN9115.2
1.0
U
U