ISL6219 Intersil Corporation, ISL6219 Datasheet - Page 11

• Manufacturer Part Number: ISL6219
• Description: Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
• Manufacturer: Intersil Corporation

The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shut-down
mode after receiving this code and will start up upon
receiving any other code.
To enable the controller, VCC must be greater than the POR
threshold; the base of PNP transistor must be greater than
1.23V; and VID cannot be equal to 11111. Once these
conditions are true, the controller immediately initiates a soft
start sequence.
SOFT-START
After the POR function is completed with V
4.38V, the soft-start sequence is initiated. Soft-Start, by its
slow rise in CORE voltage from zero, avoids an over-current
condition by slowly charging the output capacitors. This
voltage rise is initiated by an internal DAC that slowly raises
the reference voltage to the error amplifier input. The voltage
rise is controlled by the oscillator frequency and the DAC
within the controller, therefore, the output voltage is
effectively regulated as it rises to the final programmed
CORE voltage value.
For the first 32 PWM switching cycles, the DAC output
remains inhibited and the PWM outputs remain in a high-
impedance state. From the 33rd cycle and for another,
approximately 150 cycles the PWM output remains low,
clamping the lower output MOSFETs to ground. The time
variability is due to the error amplifier, sawtooth generator and
comparators moving into their active regions. After this short
interval, the PWM outputs are enabled and increment the
PWM pulse width from zero duty cycle to operational pulse
width, thus allowing the output voltage to slowly reach the
CORE voltage. The CORE voltage will reach its programmed
value before the 2048 cycles, but the PGOOD output will not
be initiated until the 2048th PWM switching cycle.
The soft-start time, t
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz has a soft-start
time of
Figure 9 shows the waveforms when the regulator is
operating at 200kHz. Note that the soft-start duration is a
function of the Channel Frequency as explained previously.
Also note the pulses on the COMP terminal. These pulses
are the current correction signal feeding into the comparator
input (see the Block Diagram).
DYNAMIC VID
The ISL6219 is capable of executing on-the-fly output-
voltage changes. At the beginning of the phase-1 switching
cycle (defined in the section entitled PWM Operation), the
ISL6219 checks for a change in the VID code. The VID code
is the bit pattern present at pins VID4-VID0 as outlined in
T
SS
SS
, is determined by an 11-bit counter
=
2048
------------ -
f
SW
11
=
8.2ms
CC
reaching
(EQ. 5)
Voltage Regulation. If the new code remains stable for
another full cycle, the ISL6219 begins incrementing the
reference by making 25mV change every two switching
cycles until it reaches the new VID code.
Since the ISL6219 recognizes VID-code changes only at the
beginnings of switching cycles, up to one full cycle may pass
before a VID change registers. This is followed by a one-
cycle wait before the output voltage begins to change. Thus,
the total time required for a VID change, t
on the switching frequency (f
(∆V
The one-cycle uncertainty in Equation 6 is due to the
possibility that the VID code change may occur up to one full
cycle before being recognized. The time required for a
converter running with f
reference-voltage change is between 30µs and 32µs as
calculated using Equation 6. This example is also illustrated
in Figure 10
.
.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
FIGURE 9. START-UP OF 3 PHASE SYSTEM OPERATING AT
ID
), and the time before the next switching cycle begins.
200kHz
---- -
f
DELAY TIME
1
S


2 V
---------------- - 1
0.025
∆
ID
–
S
= 500kHz to make a 1.5V to 1.7V


<
S
t
), the size of the change
DV
≤
VIN = 12V
---- -
f
1
S



2 V
---------------- -
0.025
∆
DV
ID
, is dependent



V COMP
PGOOD
VCORE
5V
VCC
(EQ. 6)