ISL6421 Intersil Corporation, ISL6421 Datasheet
ISL6421
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ISL6421 Summary of contents
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... Voltage Regulator with I C Interface for Advanced Satellite Set-top Box Designs The ISL6421 is a highly integrated solution for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise block (LNB). This device is comprised of a current-mode boost PWM and a low-noise ...
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... Pinout PGND SGND SEL18V BYPASS PGND GATE Typical Application Schematic VIN = 8V TO 14V + C1 C2 1µF 56µF VOUT 2 ISL6421 ISL6421ER (32 LEAD 5X5 QFN) TOP VIEW 56µF 33µ 1µF ...
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Block Diagram OVERCURRENT COUNTER PROTECTION LOGIC SCHEME 1 LOGIC GATE Q PGND ILIM CS AMP CS COMPENSATION COMP FB VSW VOUT ON CHIP VCC LINEAR UVLO SGND POR SOFT-START SEL18V OLF DCL PWM OC CLK S ISEL EN ENT OTF ...
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... Dynamic Overload Protection On Time 22kHz TONE Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time 4 ISL6421 Thermal Information Thermal Resistance QFN Package (Notes 1, 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range . . . . . . . . . . -40 Maximum Lead Temperature (Soldering 10s 300 (SOIC - Lead Tips Only) ...
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... Temperature Shutdown Hysteresis NOTES: 3. Internal Digital Soft-start 4. Voltage programming signals VSEL and LLC are implemented via the 450mA. 5. Guaranteed by Design. 5 ISL6421 - +85 C, unless otherwise noted. Typical values are 12mA, unless otherwise noted. See software description section for I ...
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... SEL18V When connected HIGH, this pin will change the output of the PWM to 18V. Functional Description The ISL6421 single output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for a low noise block (LNB) are available simultaneously in any output configuration ...
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... SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stage of ISL6421 will have an open drain/open collector in order to perform the wired-AND function. Data on the I , OFF transferred up to 100kbits/s in the standard-mode 400kbits/s in the fast-mode. The level of logic “ ...
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... SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6421 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW. SCL ...
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... Received Data ( Bus Read Mode The ISL6421 can provide to the master a copy of the System 2 Register information via the I C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set the following Master generated clock bits, the ISL6421 issues a byte on the SDA data bus line (MSB transmitted first) ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 ISL6421 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...