ISL6421 Intersil Corporation, ISL6421 Datasheet - Page 8

• Manufacturer Part Number: ISL6421
• Description: Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs
• Manufacturer: Intersil Corporation

START
SDA
SCL
Byte Format
Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6421 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
System Register Format
•
•
All bits reset to 0 at Power-On
R, W = Read and Write bit
R = Read-only bit
SR
0
0
0
0
0
0
0
FIGURE 3. ACKNOWLEDGE ON THE I
R, W
R, W
SR1
SR2
DCL
MSB
1
ISEL1
1
1
1
1
1
1
1
2
ENT1
R, W
R, W
0
1
8
DCL
X
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
LLC1
0
0
0
1
1
8
ACKNOWLEDGE
2
VSEL1
C BUS
TABLE 3. SYSTEM REGISTER 1 (SR1)
TABLE 4. SYSTEM REGISTER 2 (SR2)
FROM SLAVE
0
0
1
0
1
R, W
R, W
X
X
9
EN1
1
1
1
1
1
1
1
ISL6421
OLF1
ENT1
R, W
R, W
X
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6421 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
Transmitted Data (
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system register (SR1) of the
ISL6421 via I
microprocessor as shown below.
SR1 is selected
Vout1 = 13V, Vboost1 = 13V + Vdrop
Vout1 = 18V, Vboost1 = 18V + Vdrop
Vout1 = 14V, Vboost1 = 14V + Vdrop
Vout1 = 19V, Vboost1 = 19V + Vdrop
22kHz tone is controlled by the DSQIN pin
22kHz tone is ON, the DSQIN input is disabled
S
read (1) or write (0) transmission) (the assigned I
address for the ISL6421 is 0001 00XX)
0
0
LLC1
R, W
R, W
X
0
2
TABLE 2. INTERFACE PROTOCOL
C bus. These will be written by the
1
0
0
I
VSEL1
2
R, W
R, W
EN2
C
0
FUNCTION
bus WRITE mode)
R/W ACK Data (8 bits) ACK P
R, W
EN1
OTF
R
OLF1
2
C slave
R
R
X