ISL6421 Intersil Corporation, ISL6421 Datasheet - Page 9

• Manufacturer Part Number: ISL6421
• Description: Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs
• Manufacturer: Intersil Corporation

Received Data (
The ISL6421 can provide to the master a copy of the System
Register information via the I
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6421 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
• Not acknowledge, stopping the read mode
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6421.
Power–On I
The I
at power-on. The I
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I
system register SR is initialized to all zeros, thus keeping the
power blocks disabled.
Once Vcc rises above the UVLO level, the POWER OK
signal given to the I
interface becomes operative and the SR can be configured
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
the Power-On reset circuit.
These bits are read as they were
after the last write operation.
DCL ISEL ENT LLC VSEL EN OTF OLF
transmission of another byte from the ISL6421.
communication.
SR
SR
0
0
0
1
2
C interface built into the ISL6421 is automatically reset
TABLE 6. READING SYSTEM REGISTERS
DCL
X
1
0
X
-
2
C Interface Reset
2
I
ISEL1
C interface block will receive a Power OK
2
2
C
C interface block will be HIGH, the I
1
1
1
X
-
Bus Read Mode)
ENT1
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION (Continued)
2
X
X
C bus in read mode. The read
9
-
0
1
2
C commands and the
LLC1
0
1
X
X
-
Tj <= 130°C, Normal
operation
Tj > 150°C, Power
blocks disabled
Iout < Imax, Normal
operation
Iout > Imax, Overload
protection triggered
VSEL1
FUNCTION
EN2
X
0
EN1
OTF
X
1
1
0
2
C
ISL6421
OLF1
X
-
(I
as (or later than) all other I
valid).
ADDRESS Pin
Connecting this pin to GND forces the chip I
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.
I
Input Logic High,
VIH
Input Logic Low,
VIL
Input Logic
Current, IIL
SCL Clock
Frequency
Dynamic current limit NOT selected
Dynamic current limit selected
PWM and Linear for channel 1 disabled
SR2 is selected; to read OTF flag.
2
2
PARAMETER
C Electrical Characteristics
C comes up with EN = 0, EN goes HIGH at the same time
“0001000”
“0001001”
VADDR
Vaddr-1
Vaddr-2
TABLE 7. ADDRESS PIN CHARACTERISTICS
TABLE 8. I
SDA, SCL
SDA, SCL
SDA, SCL;
0.4V < Vin < 4.5V
CONDITION
TEST
2.7V
MIN
FUNCTION
FUNCTION
0V
2
2
C SPECIFICATIONS
C data for the PWM becomes
MIN
0
TYP
-
-
0.7 x V
0.3 x V
100kHz
2
TYP
C interface
DD
DD
MAX
2.0V
5.0V
400kHz
10µA
MAX