ISL6540A Intersil Corporation, ISL6540A Datasheet - Page 16

• Manufacturer Part Number: ISL6540A
• Description: Single-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

current paths on the SS pin and locate the capacitor, C
close to the SS pin (as described earlier) as the internal
current source is only 37μA. Provide local decoupling
between PVCC and PGND pins as described earlier. Locate
the capacitor, C
PHASE pins.
Compensating the Converter
The ISL6540A single-phase converter is a voltage-mode
controller. This section highlights the design considerations for
a voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
(V
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a
pulse-width modulated wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
DC gain, given by D
output filter, with a double pole break frequency at F
zero at F
represent the total output capacitance and its equivalent
series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6540A) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F
The equations that follow relate the compensation network’s
F
LC
OUT
FIGURE 9. COMPENSATION CONFIGURATION FOR
=
) is regulated to the reference voltage, VREF, level.
---------------------------
2π
C
CE
R
3
⋅
3
1
. For the purpose of this analysis C and ESR
L C
0
OUT
; typically 0.1 to 0.3 of F
⋅
ISL6540A WHEN USING DIFFERENTIAL REMOTE
SENSE
BOOT
/V
COMP
MAX
R
R
as close as practical to the BOOT and
1
2
V
. This function is dominated by a
F
C
CE
IN
2
/V
C
16
=
1
OSC
-------------------------------- -
2π C ESR
⋅
, and shaped by the
COMP
VMON
1
SW
FB
⋅
) and adequate
1
-R
0dB
ISL6540A
3
, C
and 180°.
LC
1
IN
-C
at the
and a
3
SS
ISL6540A
poles, zeros and gain to the components (R
and C
locating the poles and zeros of the compensation network:
1. Select a value for R
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
value for R
setting the output voltage to be equal to the reference set
voltage as shown in Figure 9, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 10), in order
to compensate for the attenuation introduced by the
resistor divider, the below obtained R
multiplied by a factor of (R
of the calculations remain unchanged, as long as the
compensated R
A small capacitor,
out noise, typically
time constant does not reduce the overall phase margin
of the design, typically this is 2x to 10x switching
frequency of the regulator. As the ISL6540A supports
100% duty cycle, d
uses feedforward compensation, as such V
R
CIRCUIT
2
PWM
3
) in Figures 9 and 10. Use the following guidelines for
=
-------------------------------------------- -
d
V
COMP
MAX
OSC
COMPENSATION DESIGN
2
HALF-BRIDGE
⋅
OSCILLATOR
V
for desired converter bandwidth (F
⋅
V
R
IN
OSC
E/A
DRIVE
1
2
⋅
⋅
R
ISL6540A
F
value is used.
F
C
2
LC
MAX
0
SEN
C
1
SEN
C
+
-
+
(1kΩ to 10kΩ, typically). Calculate
VREF
2
-
in Figure 10, can be added to filter
C
equals 1. The ISL6540A also
is chosen so the corresponding
1
OS
FB
PHASE
UGATE
LGATE
VMON
VSEN-
VSEN+
+R
EXTERNAL CIRCUIT
FB
R
)/R
3
V
IN
R
2
OS
C
1
1
SEN
value needs be
, R
C
. The remainder
L
3
2
OSC
, R
DCR
R
March 12, 2007
V
3
ESR
OS
OUT
0
, C
C
is equal
). If
R
FB
FN6288.2
1
, C
2
,