ISL6540A Intersil Corporation, ISL6540A Datasheet - Page 17

• Manufacturer Part Number: ISL6540A
• Description: Single-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
As before when tieing VFF to VIN terms in the above
equations can be simplified as follows:
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 11 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
G
D
------------------------------ -
4. Calculate R
2. Calculate C
3. Calculate C
MOD
MAX
G
G
V
FB
CL
to 0.16 multiplied by the voltage at the VFF pin. When
tieing VFF to V
R
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
C
C
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R
C
OSC
2
1
2
3
3
f ( )
f ( )
f ( )
⋅
V
=
=
=
=
=
IN
=
=
0.16 R
----------------------------------
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
--------------------- -
------------------------------------------------ -
2π R
=
F
----------- - 1
F
SW
SW
LC
D
------------------------------ -
--------------------------------------------------- - ⋅
s f ( ) R
------------------------------------------------------------------------------------------------------------------------ -
(
G
=
R
1
⋅
⋅
⋅
1
MAX
MOD
F
1
-------------------------- -
0.16 V
⋅
+
). F
V
–
P2
+
LC
1
2
2
2
3
3
1 V
OSC
⋅
s f ( ) R
such that F
s f ( ) R
1
⋅
⋅
⋅
such that F
such that F
1
⋅
FB
1
SW
0.5 F
C
is placed below F
0.7 F
⋅
f ( ) G
C
⋅
1
⋅
IN
V
F
1
1
⋅
⋅
IN
) and closed-loop response (G
IN
⋅
0
(
⋅
⋅
LC
⋅
⋅
IN
represents the regulator’s switching
C
the above equation simplifies to:
F
1
3
⋅
CE
2
1
LC
SW
+
FB
⋅
---------------------------------------------------------------------------------------------------------- -
1
(to adjust, change the 0.5 factor to
=
⋅
+
C
s f ( )
C
+
f ( )
–
C
3
6.25
Z1
1
s f ( )
)
P1
1
2
Z2
⋅
)
⋅
17
⎛
⎜
⎝
is placed at a fraction of the F
(
1
is placed at F
is placed at F
R
⋅
(
1
+
ESR
+
where s f ( )
s f ( ) R
1
SW
CE
R
+
3
s f ( ) ESR C
⋅
/F
+
) C
(typically, 0.5 to 1.0
⋅
DCR
,
LC
P2
2
MOD
⋅
⋅
3
, the lower the F
⎛
⎜
⎝
lower in frequency
LC
CE
LC
-------------------- -
C
C
) C
), feedback
=
1
⋅
1
).
. Calculate C
.
+
⋅
2π f j
⋅
C
C
+
2
2
s
⋅ ⋅
CL
⎞
⎟
⎠
2
⎞
⎟
⎠
f ( ) L C
):
⋅
LC
⋅
Z1
ISL6540A
3
,
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 11 by adding the modulator gain,
G
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, F
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
F
F
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Z1
Z2
MOD
0
=
=
LOG
------------------------------ -
2π R
-------------------------------------------------
2π
(in dB), to the feedback compensation gain, G
20
log
⋅
⋅
(
1
R
⎛
⎝
2
R2
------- -
R1
1
⋅
+
C
1
⎞
⎠
R
1
3
) C
F
Z1
⋅
F
F
P2
LC
3
Z2
against the capabilities of the error
SW
F
F
F
F
CE
P1
P2
P1
.
CL
=
=
F
0
, is constructed on the
-------------------------------------------- -
2π R
------------------------------ -
2π R
F
20
P2
⋅
⋅
log
G
1
2
3
CL
COMPENSATION GAIN
D
---------------------------------- -
OPEN LOOP E/A GAIN
⋅
⋅
1
CLOSED LOOP GAIN
G
MAX V
-------------------- -
C
C
C
V
MODULATOR GAIN
MOD
1
3
1
OSC
FREQUENCY
+
⋅
⋅
C
C
2
2
IN
March 12, 2007
G
FB
FB
FN6288.2
(in