AD6426 Analog Devices, AD6426 Datasheet - Page 14
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AD6426
Manufacturer Part Number
AD6426
Description
Enhanced GSM Processor
Manufacturer
Analog Devices
Datasheet
1.AD6426.pdf
(50 pages)
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GENERAL CONTROL
Clocks
Clock Input
The AD6426 requires a single 13 MHz, low level clock signal,
which has to be provided at the pin CLKIN. For proper
operation a signal level of 250 mV
This feature eases system design and reduces the need for
external clock buffering. Only minimal external components
are required as shown in Figure 4.
The internal clock buffer can accept any regular waveform as
long as it can find voltage points in the signal, for which a
50% duty cycle can be determined. This condition is met for
sinewaves, triangles, or slew-limited square waves. Dedicated
circuitry searches for these points and generates the respective
bias voltage internally.
The external capacitor (1nF) decouples the bias voltage of the
clock signal generated by the oscillator from the internally
generated bias voltage of the clock buffer circuitry.
The LC-filter shown is optional. It ensures, that the input
signal is “well behaved” and sinusoidal. Additionally it filters
out harmonics and noise, that may be on top of the pure 13
MHz signal.
Clock Output
The input clock drives both the H8 and the Channel Codec
directly. A gated version, controlled by the Output Clock
Enable flag in CC Control Register 45, drives the CLKOUT
pin of the EVBC interface. The stand-by state of CLKOUT is
logic zero. The CLKOUT output will be active on reset.
Slow Clocking
To reduce power consumption of AD20msp425 solutions, a
new slow clocking scheme has been designed into the
AD6426. This scheme allows the VCTCXO to be powered
down between paging blocks during Idle Mode and for a
32.768kHz oscillator to keep the time reference during this
period. Only a common 32.768kHz watch crystal is required to
take advantage of this scheme. As in previous generations,
power consumption is also kept to a minimum using
asynchronous design techniques and by stopping all
unnecessary clocks.
Layer 1 software and logic built into the AD6426 are
responsible for maintaining synchronization and calibration of
the slow clock and ensure the validity of the time reference
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
Preliminary Technical Information
VCTCXO
13 MHz
OUT
Figure 4. Clock Input Circuitry
13 MHz Filter
Optional
2.2 H
68 pF
PP
minimum is required.
1nF
CLKIN
AD6422
- 14 -
under all circumstances. The active-high OSC13MON output
is prevented from becoming inactive if the 32.768kHz signal is
not present. The following table describes the functionality of
the relevant pins.
The following table lists the recommended specification for a
32kHz crystal.
Real Time Clock and Alarm
The AD6426 provides a simple Real Time Clock (RTC) using
the 32.768kHz clock input. A 40 bit counter allows for more
than one year of resolution. The RTC module contains a
32.768kHz on chip oscillator buffer designed for very low
power consumption and a set of registers for a timer, alarm,
control and status functions.
The RTC circuit is supplied by two sources; a VDDRTC
supply pin and the main system VDD. It is the handset
designer’s responsibility to provide suitable switching
between the main system VDD and a backup supply to ensure
the RTC module is permanently powered.
The VDDRTC pin is intended to interface to a backup battery
circuit or charge holding network in order for the RTC to
maintain timing accuracy when the main battery is removed
and the handset is powered down.
The user can set an alarm time at which the handset powers
up. If an alarm time is set, the current time matches the alarm
time, and the power on alarm feature is enabled, the handset is
powered up by asserting the PWRON pin for a period of
approximately 2 seconds.
Parameter
ESR
Shunt Capacitance
Load Capacitance
Turnover
Temperature (T
Parabolic Curvature
Constant (K)
Name
OSCIN
OSCOUT
OSC13MON
PWRON
o
)
I/O
O
O
O
I
Min
6
Function
32.768kHz Crystal Input
32.768kHz Oscillator
Output
13 MHz Oscillator Power
Control
Power ON/OFF Control
Confidential Information
0.040
Typ
12.5
25
Max
50
30
2
AD6426
ppm/°C
Units
k
pF
pF
°C