AD6426 Analog Devices, AD6426 Datasheet - Page 16

• Manufacturer Part Number: AD6426
• Description: Enhanced GSM Processor
• Manufacturer: Analog Devices

Wait
The H8 microprocessor WAIT input signal can be controlled
externally by programming the FLASHPWD pin to switch to
the WAIT input function. Setting the flag FLASHPWD Disable
in CC Control Register 77 to 1 and GPO11 Select to 0,
transforms the FLASHPWD output pin into a WAIT input pin.
External devices driving WAIT must drive high on reset and
until the software has changed the FLASHPWD pin to the
WAIT function.
Automatic Booting
To allow download of FLASH memory code into the final
system, the AD6426 provides a small dedicated routine to
transfer code through the Data Interface into the FLASH
memory. This routine is activated by asserting the
BOOTCODE pin.
Power Control
The AD6426 and Layer 1 software is optimized to minimize
the mobile radio power consumption in all modes of operation.
Two power control registers are dedicated for activating and
deactivating functional modules:
INTERFACES
The GSM Processor provides eleven external interfaces for
dedicated purposes:
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
Preliminary Technical Information
Bit
Bit
2
1
0
5
4
2
1
POWER CONTROL INTERNAL CC Control
Register 44
Synthesizer Interface Power Enable
DSP Interface Power Enable
Encryption Power Enable
POWER CONTROL EXTERNAL CC Control
Register 45
Output Clock Enable (will reset to 1)
General Purpose Power Control
DSP Power Control
Radio Power Control
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Test Interface
11. Debug Interface
Memory Interface
EEPROM Interface
SIM Interface
Accessory Interface
Universal System Connector Interface
Keypad / Backlight / Display Interface
Battery ID Interface
Voiceband/Baseband Converter (EVBC)
Interface
Radio Interface
- 16 -
Memory Interface
The memory interface of the AD6426 serves two purposes.
Primarily, it provides the data, address, and control lines for
the external memories (RAM and ROM / FLASH Memory).
Secondly, the data and address lines are used to interface with
the display. The pins of the memory interface are listed in
Table 5.
The HWR and LWR pins can be configured to function as
UBS and LBS, respectively, by setting the SRAM16 bit (bit 0)
of the MEMIF H8 Peripheral Control Register 80. This bit is
reset at power-up. When configured as UBS and LBS, these
pins facilitate access of 16-bit SRAM in conjunction with the
Read/Write Strobes.
The pin FLASHPWD is automatically asserted low when the
H8 enters the Software Standby Mode, and de-asserted when
an interrupt causes the H8 to exit the Software Standby Mode.
This allows the use of “deep power down mode” for certain
FLASH memories. Also the entire data bus is driven low
during software standby mode.
EEPROM Interface
The AD6426 provides a 3-wire interface to an external
EEPROM by using three GPIOs of the control processor.
Table 6 shows the functionality of these three pins.
Name
ADD20 : 0
DATA15:0
RD
HWR
LWR
WR
RAMCS
ROMCS
FLASHPWD
Name
EEPROMDATA
EEPROMCLK
EEPROMEN
Table 6. EEPROM Interface
Table 5. Memory Interface
I/O
I/O
O
O
O
O
O
O
O
O
I/O
I/O
O
O
Function
Address bus
Data bus
Read strobe
High write strobe / Upper
Byte Strobe
Low write strobe / Lower
Byte Strobe
Write Strobe
RAM chip select
FLASH / ROM chip select
FLASH Powerdown
Confidential Information
Function
EEPROM data
EEPROM clock
EEPROM enable
AD6426