AD6426 Analog Devices, AD6426 Datasheet - Page 20

• Manufacturer Part Number: AD6426
• Description: Enhanced GSM Processor
• Manufacturer: Analog Devices

Serial Display Interface
The serial display interface is compatible with display drivers
by Motorola and Seiko-Epson. The display driver by Motorola
uses an SPI serial bus which requires an inverted or delayed
clock in comparison to the Seiko-Epson type display driver.
In the Motorola mode the data is delayed by one half clock
cycle such that the data is driven on the rising edge of SCLK
instead of on the falling edge.
The serial display interface consists of four pins; a serial data
output (DISPD0), clock (DISPCLK), chip enable (DISPEN)
and address (DISPA0). These pins are multiplexed with
GPIO4, GPIO3, LCDCTL and DISPLAYCS.
Bit 1 (DISP) of the MEMIF H8 Peripheral Control Register 80
controls the configuration of the display interface. With this
set to 0, the parallel display interface is used. Setting this bit
to one enables the use of the serial display interface. This bit
is set to 0 on reset.
Bit 4 (SERDISP MODE) of the SERDISPLAY/NMI H8
Peripheral Control Register 106 controls the serial display
mode. The default setting is Seiko-Epson mode. To enable the
Motorola mode the user must set the register bit to ONE.
Display Reset
No dedicated pin is used to reset the display sub system. It is
recommended that the VBCRESET pin is used for this
function by connecting the Reset input on the display and the
Reset input on the VBC to the AD6426 VBCRESET pin. The
VBC and display cannot be reset independently. However one
of the GPIO pins can be used to reset the display separately.
Battery ID Interface
The AD6426 provides a single-wire interface compatible with
the Dallas Semiconductor
Identification chip. The communication protocol supports three
operations: RESET, READ and WRITE. These operations
permit reading the present status off the battery and writing
updated information to the ID chip. The interface is available
as the BATID function multiplexed on the GPIO5 pin.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
Preliminary Technical Information
DS2434or DS2435 Battery
- 20 -
Bit 3 (DALLAS EN) of the MEMIF H8 Peripheral Control
Register 80 controls the enabling of the battery ID interface
module. Setting this bit to zero enables the interface, resetting
the bit disables it. This bit is set to one on reset.
EVBC Interface
The AD6426 interfaces directly to the Enhanced Voiceband
Baseband Converter AD6425 through the pins shown in
12
the Auxiliary Serial Port (ASPORT), the Baseband Serial Port
(BSPORT) and the Voiceband Serial Port (VSPORT). Layer 1
software enables/disables the clock output in order to reduce
system power consumption to a minimum if operation of the
AD6425 is not required. Figure 6 shows the interface between
the AD6426 and the AD6425 as well as to the AD6432 IF
chip.
ASPORT
BSPORT
VSPORT
.The communication is performed through three serial ports:
Name
CLKOUT
EVBCRESET
ASDO
ASOFS
ASCLK
ASDI
BSDO
BSOFS
BSCLK
BSIFS
BSDI
VSDO
VSDI
VSCLK
VSFS
Table 12. EVBC Interface
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Confidential Information
Function
Clock Output to EVBC
Reset Output to EVBC
Data Output
Output Framing Signal
Clock Output
Data Input
Data Output
Output Framing Signal
Clock Input
Input Framing Signal
Data Input
Data Output
Data Input
Clock Input
Input/Output Framing Signal
AD6426
Table