T71L6816A Taiwan Memory Technology, T71L6816A Datasheet - Page 11

• Manufacturer Part Number: T71L6816A
• Description: Sixteen-port 10/100 Switch
• Manufacturer: Taiwan Memory Technology

DataSheet4U.com
www.DataSheet4U.com
DataSheet
4
U
.com
tm
For example, if we write VLAN_1[15:8] as “0xff”, VLAN_1[7:0] as “0x00”, VLAN_2[15:8] as
“0x0f” and VLAN_2[7:0] as “0xf0”, the T71L6816A will recognize that VLAN group 1 contains
port 15 to port 8, VLAN group 2 contains port 11 to port 4 and VLAN group 3 contains
port 3 to port 0.
3.14 Port-based Trunking
Trunking scheme allows more than two ports to be connected in parallel between two switchs
to increase the traffic bandwidth. The T71L6816A supports up to four ports to form the
trunking backbone with four different mode to balance traffic load and maximum 400Mbps
of data rate is allowed. Also, the T71L6816A supports the link-redirect scheme for trunking
so that the T71L6816A can backup the link circuit automatically while one link
is down and restore the circuit after the circuit is up.
3.15 Port Monitoring
The T71L6816A provides the simple network monitoring scheme for persons who need to snoop
the traffic input from one specific port. By set “SnoopEn” bit in EEPROM, beyond of the
normal forwarding, the T71L6816A will make a duplication of any packet input from the
specified port defined in SPID and forward this copy to another specific port defined
in MPID, i.e., only one pair of snooping/monitoring port can be defined.
3.16 Queue Priority
There are four queues supported by T71L6816A with different priorities for every output
port. In general, the T71L6816A will treat all output packets as the same and put them
into one queue with lowest priority. However, if any packet which contains the 802.1Q
tagging with 3-bit priority value larger than 0 or comes from one port defi ned as high
priority is found, those packets will be put into other three output queues with more
higher priorities. The T71L6816A will use weighted round-robin method to serve every
output queue for each port that has packets in queues.
3.17 Interface of PHY management
The T71L6816A supports the PHY management through two signal lines, MDC and MDIO. The
T71L6816A will write physical abilities to the register 4 and register 5 of connected
PHYs and restart the auto -negotiation process by polling each PHYs with PHY address
Taiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
CH
TE
DataSheet4U.com
P. 11
Preliminary T71L6816A
Publication Date:Jun. 2001
Revision:0.A