T71L6816A Taiwan Memory Technology, T71L6816A Datasheet - Page 15

• Manufacturer Part Number: T71L6816A
• Description: Sixteen-port 10/100 Switch
• Manufacturer: Taiwan Memory Technology

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4.2 Pin Description
REFCLK
TXD_A[1:0]
TXD_B[1:0]
TXD_C[1:0]
TXD_D[1:0]
TXD_E[1:0]
TXD_F[1:0]
TXD_G[1:0]
TXD_H[1:0]
TXD_I[1:0]
TXD_J[1:0]
TXD_K[1:0]
TXD_L[1:0]
TXD_M[1:0]
TXD_N[1:0]
TXD_O[1:0]
TXD_P[1:0]
RXD_A[1:0]
RXD_B[1:0]
RXD_C[1:0]
RXD_D[1:0]
RXD_E[1:0]
RXD_F[1:0]
RXD_G[1:0]
RXD_H[1:0]
RXD_I[1:0]
RXD_J[1:0]
RXD_K[1:0]
RXD_L[1:0]
RXD_M[1:0]
RXD_N[1:0]
RXD_O[1:0]
RXD_P[1:0]
Taiwan Memory Technology, Copy-Right reserved.
Change to products or specifications without notice.
Symbol
CH
TE
I/O type
O
I
I
180, 181
186, 187
193, 194
199, 200
206, 207
6, 7
12, 13
18, 19
24, 25
30, 31
38, 39
44, 45
50, 51
56, 57
62, 63
70, 71
176, 177
182, 183
189, 190
195, 196
202, 203
208, 3
8, 9
14, 15
20, 21
26, 27
34, 35
40, 41
46, 47
52, 53
66, 67
166
58, 59
Pin Number
RMII Interfaces
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TXD[1:0] must operate synchronously with respect
RXD[1:0] must operate synchronously with respect
reference for CRSDV, RXD[1:0], TXEN and TXD[1:0]
Reference Clock .
Reference clock with 50MHz to provide the timing
Transmit Data .
Receive Data .
period while CRSDV is high.
to REFCLK and the TXD[1:0] will be accepted by
PHY transmission when TXEN is asserted.
to REFCLK and the RXD[1:0] will transfer 2 -bit
data recovered from PHY to MAC on every REFCLK
P. 15
Preliminary T71L6816A
Function
Publication Date:Jun. 2001
Revision:0.A