T4312816A Taiwan Memory Technology, T4312816A Datasheet
T4312816A
Related parts for T4312816A
T4312816A Summary of contents
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... Preliminary T4312816A SDRAM The T4312816A is 134,217,728 bits with high performance ...
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... TM Technology Inc. reserves the right to change products or specifications without notice. D ata Input R egister olum n D ecoder Latency & Burst Length Program m ing R egister Tim ing Register Preliminary T4312816A W E L(U)D QM Publication Date: APR. 2003 Revision: 0 ...
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... N.C/RFU Connection/Reserved for Future Use TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T4312816A INPUT FUNCTION Active on the positive going edge to sample all input. Disables or enables device operation by masking or enabling all input except CLK,CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. ...
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... 0.3V , all other pin are not under test = 0V OUT DD . Symbol C CLK C ADD C OUT Preliminary T4312816A Value -1.0 to 4.6 -1 +70 -55 to +150 Typ Max. Unit 3.3 3.6 V 3.0 V + 1.5 uA Min Max 2 ...
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... P. 5 Preliminary T4312816A Test Condition Burst Length = (min) , (min), CKE V (max), =15ns ...
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... TM Technology Inc. reserves the right to change products or specifications without notice Value 2.4 / 0.4 1 1.4 See Fig.2 VOH(DC )=2.4,IOH=-4m A VOL(DC )=0.4,IOL=4mA P. 6 Preliminary T4312816A Unit Output ZO=50 ohm (Fig.2)AC Output Load Circuit Publication Date: APR. 2003 Revision: 0.B Vtt=1.4v 50 ohm 30pf ...
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... In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data BL-2 clocks. TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T4312816A Speed Version Symbol -6 -7 ...
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... If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns & longer than 1ns,transient time compensation should be considered, i.e.,[(tr+tf)/2-1]ns should be added to the parameter. TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T4312816A -6 -7 Symbol Min Max ...
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... CAS Frequency Latency 100MHz(10.0ns) 2 83MHz(12.0ns) 2 75MHz(13.0ns) 2 66MHz(15.0ns) 2 60MHz(16.7ns Note : 1. 16.7ns is recommended for T4312816A RDL 2. Clock count formula : clock TM Technology Inc. reserves the right to change products or specifications without notice RAS RP RRD 60ns 42ns 15ns ...
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... Use in future Vender Specific Mode Register Set Burst length Wrap type Latency mode P.10 Preliminary T4312816A v = Valid x = Don’t care Bit2-0 WT=0 WT=1 000 1 1 001 2 2 010 4 4 011 8 8 100 R R 101 R R 110 ...
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... Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue mode register set command to initalize the mode register. Cf.) Sequence of 4 & regardless of the order. TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T4312816A Sequential Addressing Sequence (decimal) 0,1 1,0 Sequential Addressing ...
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... (V=Valid , X=Don’t Care , H=Logic High , L=logic Low BA0~BA1 : Program keys.(@MRS after the end of burst. RP P.12 Preliminary T4312816A BA / 0,1 A11 Row Address ...
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... Bs Bs *Note3 *Note3 SRC SLZ Read W rite P.13 Preliminary T4312816A *Note2. *Note4 *Note2 *Note3 *Note4 Rb Qc Read Row Active Precharge Publication Date: APR. 2003 18 19 :Don't care ...
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... X TMemory Technology Inc. reserves the right to change products or specifications without notice. Active & Read/Write Bank A Bnak B Bank C Bnak D Operation precharge 0 Bank A 0 Bank B 1 Bank C 1 Bank D X All Bamks P.14 Preliminary T4312816A /AP in read/wirte command. 10 Publication Date: APR. 2003 Revision: 0.B ...
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... P.15 Preliminary T4312816A ...
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... +CAS latency-1)+ CC RCD P.16 Preliminary T4312816A ...
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... RDL P.17 Preliminary T4312816A ...
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... P.18 Preliminary T4312816A ...
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... P.19 Preliminary T4312816A ...
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... P.20 Preliminary T4312816A ...
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... before internal precharge start. RAS P.21 Preliminary T4312816A ...
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... P.22 Preliminary T4312816A ...
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... P.23 Preliminary T4312816A ...
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... RDL P.24 Preliminary T4312816A Publication Date: APR ...
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... ‘High’ at MRS (Mode Register Set). 9 P.25 Preliminary T4312816A ...
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... tiv try prior to Row active command. SS P.26 Preliminary T4312816A ...
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... P.27 Preliminary T4312816A ...
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... Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. TM Technology Inc. reserves the right to change products or specifications without notice. Auto Refresh Cycle i fre sh P.28 Preliminary T4312816A ...
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... Dimension in inch Max Min Nom Max 1 0.047 0.6 0.016 0.020 0.024 - 0.006 0.40 0.009 0.012 0.016 - 0.0315 0.15 0.002 0.004 0.006 22.62 0.871 0.875 0.905 11.96 0.455 0.463 0.471 10.26 0.396 0.400 0.404 P.29 Preliminary T4312816A Publication Date: APR. 2003 Revision: 0.B ...