SL20T0081 System Logic Semiconductor, SL20T0081 Datasheet - Page 15

Manufacturer Part Number

SL20T0081

Description

SLS System Logic Semiconductor

Manufacturer

System Logic Semiconductor

Datasheet

1.SL20T0081.pdf (56 pages)

SLS System Logic Semiconductor

Data Transfer

MPU to internal RAM, data is automatically transferred the bus holder to the RAM as shown in figure 4. And when

reading data from internal RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read)

and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means

that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is

executed. Therefore, the data of the specified address cannot be output with the read display data instruction right

after the address sets, but can be output at the second read of data.

Figure 4. Write Timing

The SL20T0081 used bus holder and internal data bus for data transfer with the MPU. When writing data from the

COLUMN ADDRESS

Internal signals

BUS HOLDER

MPU signals

D7 ~ D0

D(N)

N+1

D(N+1)

N+2

D(N+2)

N+3

D(N+3)

SL20T0081

N+4