SL20T0081 System Logic Semiconductor, SL20T0081 Datasheet - Page 20
SL20T0081
Manufacturer Part Number
SL20T0081
Description
SLS System Logic Semiconductor
Manufacturer
System Logic Semiconductor
Datasheet
1.SL20T0081.pdf
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SLS System Logic Semiconductor
Oscillator
the voltage converter and display timing generation circuit. The oscillator circuit is only enabled when MS=“H’ and
CLS=“H”. When on-chip oscillator is not used, CLS pin must be “L”condition. In this time, external clock must be input
from CL pin.
Display Timing Generator Circuit
clock, generates a clock to the line counter and a latch signal to the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the display
data latch circuit in synchronization with display clock. The display data which is read to the LCD driver is completely
independent of the access to the display data RAM from the microprocessor. The LCD AC signal, SYNC is generated
from the display clock. 2-frame AC driver waveforms with internal timing signal are shown in figure 8.
shows the SYNC, CL, and DISP status.
Table 6. Master and Slave Timing Signal Status
This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in
This circuit generates some signals to be used for displaying LCD. The display clock, CL generated by oscillation
In a multiple chip configuration, the slave chip requires the SYNC, CL and DISP signals from the master. Table 6
Operation mode
Master
Slave
OFF(external clock used)
ON(internal clock used)
Oscillator
-
Output
Output
SYNC
Input
Output
Input
Input
CL
SL20T0081
Output
Output
DISP
Input
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