MAC7100CVF Motorola, MAC7100CVF Datasheet - Page 18

• Manufacturer Part Number: MAC7100CVF
• Description: MAC7100 Microcontroller Family Hardware Specifications
• Manufacturer: Motorola

Electrical Characteristics
3.8.6
Table 21 summarizes several startup characteristics explained in this section. Refer to the MAC7100
Microcontroller Family Reference Manual (MAC7100RM/D) for a detailed description of the startup
behavior.
3.8.6.1
The release level V
V
releasing the POR or LVR reset, the oscillator and the clock quality check are started. If after a time t
no valid oscillation is detected, the MCU will start using the internal self-generated clock. The fastest startup
time possible is given by t
3.8.6.2
The SRAM contents integrity is guaranteed if the PORF bit in the CRGFLG register is not set following a
reset operation.
3.8.6.3
When external reset is asserted for a time greater than PW
and the CPU starts fetching the reset vector without doing a clock quality check, if there was stable
oscillation before reset.
3.8.6.4
The MCU can be returned to run mode from the stop mode by an external interrupt. A clock quality check
is performed in the same manner as for POR before releasing the clocks to the system.
3.8.6.5
Recovery from pseudo stop and doze modes are essentially the same, since the oscillator is not stopped in
either mode. The controller is returned to run mode by internal or external interrupts or other wakeup events
in the system. After t
continues to execute code if the wakeup event was not an interrupt.
18
Num C
K1
K2
K3
K4
K5
K6
LVRA
D Reset input pulse width, minimum input time
D Startup from Reset
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
T POR release level
T POR assert level
is derived from the V
Startup
Power On and Low Voltage Reset (POR and LVR)
SRAM Data Retention
External Reset
Stop Recovery
Pseudo Stop and Doze Recovery
PORR
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MAC7100 Microcontroller Family Hardware Specifications
wrs
, the CPU fetches an interrupt vector if the wakeup event was an interrupt, or
and the assert level V
uposc
Freescale Semiconductor, Inc.
Rating
DD
For More Information On This Product,
(refer to Table 17).
2.5 supply. They are also valid if the device is powered externally. After
Table 21. CRG Startup Characteristics
Go to: www.freescale.com
PORA
are derived from the V
PW
Symbol
V
PW
V
RSTL
n
t
PORR
PORA
WRS
RST
RSTL
IRQ
, the CRG module generates an internal reset
0.97
Min
192
—
20
—
2
DD
2.5 supply. The assert level
Typ
—
—
—
—
—
—
Max
2.07
196
—
—
—
14
MOTOROLA
CQOUT
Unit
n
t
t
ns
osc
cyc
V
V
osc