T4312816A Taiwan Memory Technology, T4312816A Datasheet - Page 7

• Manufacturer Part Number: T4312816A
• Description: 8M x 16 SDRAM
• Manufacturer: Taiwan Memory Technology

OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted)
Note:
TM Technology Inc. reserves the right
to change products or specifications without notice.
Row active to row active delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
RAS to CAS delay
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
1. The minimum number of clock cycles is determined by dividing the minimum time required
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.
with clock cycle time and then rounding off to the next higher integer.
CH
TE
Parameter
t
t
t
t
t
t
t
t
t
t
RRD
RCD
RP
RAS
RAS
RC
CDL
RDL
BDL
CCD
CAS latency=3
CAS latency=2
(min)
(min)
Symbol
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
P. 7
12
15
15
42
60
-6
Speed Version
14
15
15
42
63
-7
Preliminary T4312816A
120K
-7.5
15
18
20
45
65
1
2
1
1
1
1
Publication Date: APR. 2003
16
20
20
48
68
-8
-10
20
20
20
50
70
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
ns
ns
ea
Revision: 0.B
Note
1
1
1
1
1
2
2
2
3
4