SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 18

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
The Change of break condition is reset by a reset error status
command in the command register
A framing error occurs when a non–zero character was seen and
that character has a zero in the stop bit position.
The parity error indicates that the receiver–generated parity was not
the same as that sent by the transmitter.
The framing, parity and received break status bits are reset when
the associated data byte is read from the RxFIFO since these “error”
conditions are attached to the byte that has the error
The overrun error occurs when the RxFIFO is full, the receiver shift
register is full, and another start bit is detected. At this moment the
receiver has 257 valid characters and the start bit of the 258
been seen. At this point the host has approximately 6/16 bit time to
read a byte from the RxFIFO or the overrun condition will be set.
The 258
and so on until an open position in the RxFIFO is seen. (“seen”
meaning at least one byte was read from the RxFIFO.)
Overrun is cleared by a use of the “error reset” command in the
command register.
The fundamental meaning of the overrun is that data has been lost.
Data in the RxFIFO remains valid. The receiver will begin placing
characters in the RxFIFO as soon as a position becomes vacant.
NOTE: Precaution must be taken when reading an overrun FIFO.
There will be 256
be one character in the receiver shift register. However it will NOT
be known if more than one “over–running” character has been
received since the overrun bit was set. The 257
and read as valid but it will not be known how many characters were
lost between the two characters of the 256
RxFIFO. In the 8-bit mode, the numbers 8 and 9 replace the
numbers 256 and 257 above.
The ”Change of break” means that either a break has been detected
or that the break condition has been cleared. This bit is available in
the ISR. The break change bit being set in the ISR and the received
break bit being set in the SR will signal the beginning of a break. At
the termination of the break condition only the change of break in
the ISR will be set. After the break condition is detected the
termination of the break will only be recognized when the RxD input
has returned to the high state for two successive edges of the 1x
clock; 1/2 to 1 bit time. (see above)
The receiver is disabled by reset or via CR commands. A disabled
receiver will not interrupt the host CPU under any circumstance in
the normal mode of operation. If the receiver is in the multi–drop or
special mode, it will be partially enabled and thus may cause an
interrupt. Refer to section on Wake–Up and the register description
for MR1 for more information.
Receiver FIFO
The receiver buffer memory is a 256 byte FIFO with three status bits
appended to each data byte. (The FIFO is then 256 11–bit ”words”).
The receiver state machine gathers the bits from the receiver shift
register and the status bits from the receiver logic and writes the
assembled byte and status bits to the RxFIFO shortly after the stop
bit has been sampled. Logic associated with the FIFO encodes the
number of filled positions for presentation to the interrupt arbitration
system. The encoding is always the number of filled positions. Thus,
a full RxFIFO will bid with the value of 255 and the Status Register
RxFULL bit is set. When empty it will not bit at all. One position
occupied bids with the value 1. An empty FIFO will not bid since no
character is available.
2000 Feb 10
Dual UART
th
character then overruns the 257
th
valid characters in the receiver FIFO. There will
th
th
and the 258
and 257
th
character received
th
reads of the
th
the 259
th
has
th
12
Normally RxFIFO will present a bid to the arbitration system
whenever it has one or more filled positions. The bits of the RxFIFO
Interrupt Offset Level (RxFIL) or the bits of the MR2(3:2) allow the
user to modify this characteristic so that bidding will not start until
one of four levels (one or more filled, 64 filled, 192 filled, full) have
been reached. As will be shown later this feature may be used to
make slight improvements in the interrupt service efficiency. A
similar system exists in the transmitter.
RxFIFO Status Bits. Status reporting modes
This description applies to the upper three bits in the ”Status
Register” These three bits are not ”in the status register”; they are
part of the RxFIFO. The three status bits at the output of the RxFIFO
are presented as the upper three bits of the status register included
in each UART.
The error status of a character, as reported by a read of the SR
(status register upper three bits) can be provided in two ways, as
programmed by the error mode control bit in the mode register:
”Character mode ” or the ”Block Mode”. The block mode may be
further modified (via a CR command) to set the status bits as the
characters enter the FIFO or as they are read from the FIFO.
In the ’character’ mode, status is provided on a character by
character basis as the characters are read from the RxFIFO: the
”status” applies only to the character at the output of the RxFIFO –
The next character to be read.
In the ’block’ mode (on entry) the status provided in the SR for these
three bits is the logical OR of the status for all characters coming to
the input of the RxFIFO since the last reset error command was
issued. In this mode each of the status bits stored in the RxFIFO are
passed through a latch as they are sequentially written to the
receiver FIFO. If any of the characters has an error bit set that latch
will set and remain set until it is reset with a “receiver reset” issued
from the command register or a chip reset is issued. The purpose of
this mode is indicating an error in the data block as opposed to an
error in a character. This mode improves receiver service efficiency.
In modern systems with low error rates, it is more efficient to ask for
retransmit of a block error data than to analyze it on a byte by byte
system.
The above paragraph describes the block mode activity as the data
is entered to the RxFIFO. Normally the status would be read only
once – at the beginning of the service to the receiver interrupt. If an
error is not set then the entire amount of data in the RxFIFO would
be read without any more reading if the receiver status. This
effectively doubles the efficiency of reading the receiver RxFIFO.
The use of the block mode on Exit passes the data and error
conditions as the RxFIFO is read. Here the final read of the status
register would be after the last byte was read from the RxFIFO. This
delays the knowledge of an error condition until after the data has
been read.
The latch used in the block mode to indicate ”problem data” is
usually set as the characters are read out of the RxFIFO. Via a
command in the CR the latch may be configured to set as error
characters are loaded to the RxFIFO. This gives the advantage of
indicating ”problem data” up to 256 (or the FIFO size) characters
earlier.
In either mode, reading the SR does not affect the RxFIFO. The
RxFIFO address is advanced only when the RxFIFO is read.
Therefore, the SR should be read prior to reading the corresponding
data character.
Objective specification
SC28L202