SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 63

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
AC CHARACTERISTICS
Vcc = 5v
2000 Feb 10
Symbol
Reset timing (See Figure 3)
t
Bus Timing
t
t
t
t
t
t
t
t
t
t
t
t
Port Timing
t
t
t
Interrupt Timing (See Figure 8)
t
Clock Timing (See Figure 9)
t
f
f
f
t
f
t
f
Transmitter Timing (See Figure 12)
t
t
Receiver Timing (See Figure 13)
t
t
68000 or Motorola bus timing (See Figure ___)
t
T
T
t
t
RES
*AS
*AH
*CS
*CH
*RW
*DD
*DA
*DF
*DI
*DS
*DH
*RWD
*PS
*PH
*PD
*IR
*CLK
*CLK
*CTC
*CTC
*RX
*RX
*TX
*TX
*TXD
*TCS
*RXS
*RXH
DCR
DAT
CSC
DCW
DAH
Dual UART
10% Ta = – 40 to +85 C unless otherwise specified
5
5
(See Figure ___)
(See Figure 7)
Parameter
Reset Pulse Width
A6–A0 setup time to RDN, WRN Low
A6–A0 hold time from RDN, WRN low
CEN setup time to RDN, WRN low
CEN Hold time from RDN. WRN Hi
WRN, RDN pulse width (Low time)
Data valid after RDN low (125 pf load) See loading table for smaller loads
RDN low to data bus active
Data bus floating after RDN or CEN high
RDN or CEN high to data bus invalid
Data bus setup time before WRN or CEN high (write cycle)
Data hold time after WRN high
High time between read and/or write cycles
Port in setup time before RDN low (Read IP ports cycle)
Port in hold time after RDN high
OP port valid after WRN or CEN high (OPR write cycle)
INTRN (or I/O(7:3)B when used as interrupts) negated from:
X1/CLK high or low time
X1/CLK frequency (7.0 to 16.2 MHz with crystal)
C/T Clk (IP2) high or low time (C/T external clock input)
C/T Clk (IP2) frequency
RxC high or low time (16X)
RxC Frequency (16X)
RxC Frequency (1x)
TxC High or low time (16X)
TxC frequency (16X)
TxC frequency (1X)
TxD output delay from TxC low (TxC input pin)
Output delay from TxC output pin low to TxD data output
RxD data setup time to RxC high
RxD data hold time from RxC high
DACKN Low (read cycle) from X1 High
DACKN Low (write cycle) from X1 High
DACKN High from CSN or IACKN high
DACKN High impedance from CSN or IACKN high
CSN or IACKN setup time to X1 high for minimum DACKN cycle
Read RxFIFO (RxRDY/FFULL interrupt)
Write TxFIFO (TxRDY interrupt)
Reset Command (delta break change interrupt)
Stop C/T command (Counter/timer interrupt
Read IPCR (delta input port change interrupt)
Write IMR (Clear of change interrupt mask bit(s))
1,2,3
8,9
8,9
(NOMINAL 5 VOLTS)
8
6
7
5,7
57
LIMITS
Min
100
10
20
0
0
15
0
0
25
0
15
0
0
30
1.0
30
0
30
0
0
30
0
50
50
10
4
Typ
18
6
11
15
17
–15
12
–20
–20
40
40
40
40
40
40
40
20
14.7
20
40
6
40
40
15
15
8
8
8
Objective specification
SC28L202
Max
40
20
60
60
60
60
60
60
60
50
50
3
50
3
60
30
20
20
10
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns