SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 31

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

1. If these bits are not 0 the characters will be stripped regardless of bits (3:2) or (1:0)
Philips Semiconductors
MR3 – Mode Register 3, A and B
NOTE:
MR3[7 & 6] Xon/Xoff Character Stripping
Control the handling of recognized Xon/Xoff or Address characters.
If set, the character codes are placed on the RxFIFO along with their
status bits just as ordinary characters are. If the character is not
loaded onto the RxFIFO, its received status will be lost unless the
receiver is operating in the block error mode, see MR1[5] and the
general discussion on receiver error handling. Interrupt processing
is not effected by the setting of these bits. See Character recognition
section.
MR3[5:4] Reserved
MR3[3:2] Xon/Xoff Processing
Control the Xon/Xoff processing logic. Auto Transmitter flow control
allows the gating of Transmitter activity by Xon/Xoff characters
received by the Channel’s receiver. Auto Receiver flow control
causes the Transmitter to emit an Xoff character when the RxFIFO
has loaded to a depth of 240 characters. Draining the RxFIFO to a
level of 128 or less causes the Transmitter to emit a Xon character.
All transmissions require no host involvement. A setting other than
2000 Feb 10
Bit 7
Xon/Xoff
transparency
0 = flow control characters
received are loaded onto
the RxFIFO
1 = flow control characters
received are not loaded
onto the RxFIFO
Dual UART
1
Bit 6
Address Recognition
transparency
0 = Address characters
received are loaded to
RxFIFO
1 = Address characters
received are not loaded onto
the RxFIFO
1
Bit 5:4
Reserved
25
b’00 in this field precludes the use of the command register to
transmit Xon/Xoff characters.
NOTE: Interrupt generation in Xon/Xoff processing is controlled by
the IMR (Interrupt Mask Register) of the individual channels. The
interrupt may be cleared by a read of the XISR, the Xon/Xoff
Interrupt Status Register. Receipt of a flow control character will
always generate an interrupt if the IMR is so programmed. The
MR0[3:2] bits have effect on the automatic aspects of flow control
only, not the interrupt generation.
MR3[1:0] Address Recognition
This field controls the operation of the Address recognition logic. If
the device is not operating in the special or ”wake–up” mode, this
hardware may be used as a general–purpose character detector by
choosing any combination except b’00. Interrupt generation is
controlled by the channel IMR. The interrupt may be cleared by a
read of the XISR, the Xon/Xoff Interrupt Status Register. See further
description in the section on the Wake Up mode.
Bit 3:2
In–band flow control
mode
00 = host mode, only the host
CPU may initiate flow control
actions through the CR
01 = Auto Transmitter flow
control
10 = Auto Receiver flow control
11 = Auto Rx and Tx flow control
Objective specification
SC28L202
Bit 1:0
Address
Recognition
control
00 = Default
01 = Auto wake
10 = Auto doze
11 = Auto wake
and auto doze