SC28L202 Philips Semiconductors, SC28L202 Datasheet - Page 46

• Manufacturer Part Number: SC28L202
• Description: Dual universal asynchronous receiver/transmitter DUART
• Manufacturer: Philips Semiconductors

Philips Semiconductors
ROPR A and ROPR B – Reset ROPR Output Port Bits (OPR A and OPR B)
ROPR [7:0] – Ones in the byte written to the ROPR will cause the
corresponding bit positions in the OPR to set to 0. Zeros have no
OPR – Output Port Register, A and B (n = A for A, n = B for B)
The output pins (I/O pins) drive the data written to this register.
This register is set by the SOPR and ROPR above.
THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS
The purpose of including previous functionality is to allow users to
call communications code that may be used in former systems.
When the registers in this lower 16–position address space is used
it will revoke programming done in the upper address space where
the addresses are duplicated. If functions have been called from
upper address space that DO NOT exist in the lower address space
they will remain active. It is therefore recommended that the “Reset
Table 7. SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0)
NOTE: The three MR Registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and
transmitter enable bits)
2000 Feb 10
Reset OPR
Bits
OPR
Address
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Dual UART
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit 7
I/O7 n
0=Pin High
1=Pin Low
Bit 7
OPR 7
1=reset bit
0=no change
READ (RDN = 0)
Mode Register A (MR0 A, MR1 A, MR2 A)
Status Register A (SR A)
Reserved
Rx Holding Register A (RxFIFO A)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper (CTPU)
Counter/Timer Lower (CTPL)
Mode Register B (MR0 B, MR1 B, MR2 B)
Status Register B (SR B)
Reserved
Rx Holding Register B (RxFIFO B)
IVR or general purpose register
Input Port (IPR) I/O(6:0) A
Start Counter Command (C/T 0)
Stop Counter Command (C/T 0)
BIT 6
I/O6 n
0=Pin High
1=Pin Low
BIT 6
OPR 6
1=reset bit
0=no
change
BIT 5
I/O5 n
0=Pin High
1=Pin Low
BIT 5
OPR 5
1=reset bit
0=no
change
BIT 4
OPR 4
1=reset bit
0=no
change
BIT 4
I/O4 n
0=Pin High
1=Pin Low
40
WRITE (WRN = 0)
Mode Register A (MR0 A, MR1 A, MR2 A)
Clock Select Register A (CSR A )
Command Register A (CR A)
Tx Holding Register A (TxFIFO A)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Upper Preset Register (CTPU)
C/T Lower Preset Register (CTPL)
Mode Register B (MR0 B, MR1 B, MR2 B)
Clock Select Register B (CSR B )
Command Register B (CR B)
Tx Holding Register B (TxFIFO B)
IVR or general purpose register
Output Port Confide. Register (OPCR) I/O(7:2) B
Set Output Port Bits Command (SOPR) I/O(7:0) B
Reset output Port Bits Command (ROPR) I/O(7:0) B
effect. This allows software to reset individual bits with our keeping a
copy of the OPR bit configuration. One register for each channel
to C92 “ command be issued before calling code written for older
devices. This is just recommended. If one wishes to enhance
previous code by using Xon/Xoff, for example, there is no restriction
against it. These registers provide the original functionality of
previous Philips DUARTs: SCN2681, SCN68681, SCC2691,
SCC68692, SC26C92 and SC28L92.
BIT 3
OPR 3
1=reset bit
0=no
change
BIT 3
I/O3 n
0=Pin High
1=Pin Low
BIT 2
OPR 2
1=reset bit
0=no
change
BIT 2
I/O2 n
0=Pin High
1=Pin Low
BIT 1
OPR 1
1=reset bit
0=no
change
BIT 1
I/O1 n
0=Pin High
1=Pin Low
Objective specification
SC28L202
BIT 0
OPR 0
1=reset bit
0=no change
BIT 0
I/O0 n
0=Pin High
1=Pin Low