STD0550 ST Microelectronics, Inc., STD0550 Datasheet - Page 11

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STD0550

Manufacturer Part Number
STD0550
Description
Matrix Display Digital TV Processor
Manufacturer
ST Microelectronics, Inc.
Datasheet
General Description
1.4.2
11/32
CLK_DATA
YCRCB[7:0]
27 MHz
NRESET
Crystal
HSYNC
VSYNC
The video display/TV system operates with a single external SDRAM that is used for the field-rate
up-conversion, text and graphic generations.The external SDRAM can be configured as a single
bank of 16/64/128 Mb (16-bit configuration) or a dual bank of 16 to 256 Mb (32-bit configuration).
Application program codes are stored in an external Flash memory and executed from the SDRAM.
Deinterlacing Modes and Progressive Scan Output
The de-interlacing can be done in the following modes:
Spatial line interpolation, using the high resolution vertical polyphase filter
Motion adaptive spatial-temporal interpolation, using the median filter
Field merging for film sources
8
Generator
Build-Up
HV Filter
Counter
Clock
Block
SDIN
TNR
Figure 5: Architectural Block Diagram
Pipeline
Pipeline
Video
OSD
TV Peripherals
TV Chassis Control
ST20 Core
YSI
CTI
Compositor
Picture
Comp.
Cursor
Plane
BG
I/Os
Block Move
30
CSA
2D
Communiction
Time Base
Generator
Output
Perfect
Engine
Digital
Video
Color
EMI4
16/32
4 to 10 bits
4 to 10 bits
4 to 10 bits
SDRAM
Hout
Vout
R
G
B
H/V
DE
DLCK
Flash
STD0550

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