UCC1580-1 Unitrode Semiconductor, UCC1580-1 Datasheet - Page 4

• Manufacturer Part Number: UCC1580-1
• Description: Single Ended Active Clamp Reset PWM
• Manufacturer: Unitrode Semiconductor

ELECTRICAL CHARACTERISTICS (cont.):
range, VDD = 12V, R1 = 18.2k, R2 = 4.41k, C
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
CLK: Oscillator clock output pin from a low impedance
CMOS driver. CLK is high during guaranteed off time.
CLK can be used to synchronized up to five other
UCC3580 PWMs.
DELAY: A resistor from DELAY to GND programs the
nonoverlap delay between OUT1 and OUT2. The delay
times, Delay1 and Delay2, are shown in Figure 1 and are
as follows:
EAIN: Inverting input to the error amplifier. The
noninverting input of the error amplifier is internally set to
2.5V. EAIN is used for feedback and loop compensation.
EAOUT: Output of the error amplifier and input to the
PWM comparator. Loop compensation components
connect from EAOUT to EAIN.
GND: Signal Ground.
LINE: Hysteretic comparator input. Thresholds are 5.0V
and 4.5V. Used to sense input line voltage and turn off
OUT1 when the line is low.
OSC1 & OSC2: Oscillator programming pins. A resistor
connects each pin to a timing capacitor. The resistor
connected to OSC1 sets maximum on time. The resistor
connected to OSC2 controls guaranteed off time. The
combined total sets frequency with the timing capacitor.
Frequency and maximum duty cycle are approximately
given by:
Maximum Duty Cycle for OUT1 will be slightly less due
to Delay1 which is programmed by R3.
OUT1: Gate drive output for the main switch capable of
sourcing up to 0.5A and sinking 1A.
Reference Section
40°C to 85°C for the UCC2580, 55°C to 125°C for the UCC1580, T
REF
Load Regulation
Line Regulation
Delay 1 = 1.1pF
Delay 2 is designed to be larger than Delay 1 by a
ratio shown in Figure 2.
Frequency
Maximum Duty Cycle
PARAMETER
R1
R3.
1.25
1
R1 1.25 R2
R2
R1
C
T
T
= 100pF, R3 = 100k, C
I
I
VDD = 10V to 14V
REF
REF
= 0
= 0mA to 1mA
Unless otherwise stated, all specifications are over the full temperature
TEST CONDITIONS
4
OUT2: Gate drive output for the auxiliary switch with
PGND: Ground connection for the gate drivers. Connect
PGND to GND at a single point so that no high frequency
components of the output switching currents are in the
ground plane on the circuit board.
RAMP: A resistor (R4) from RAMP to the input voltage
and a capacitor (CR) from RAMP to GND programs the
feedforward ramp signal. RAMP is discharged to GND
when CLK is high and allowed to charge when CLK is
low. RAMP is the line feedforward sawtooth signal for the
PWM comparator. Assuming the input voltage is much
greater than 3.3V, the ramp is very linear. A flux
comparator compares the ramp signal to 3.3V to limit the
maximum allowable volt-second product:
REF: Precision 5.0V reference pin. REF can supply up to
5mA to external circuits. REF is off until VDD exceeds 9V
(-1 and -3 versions) or activates the 15V clamp (-2 and -4
versions) and turns off again when VDD droops below
8.5V. Bypass REF to GND with a 1 F capacitor.
SHTDWN: Comparator input to stop the chip. The
threshold is 0.5V. When the chip is stopped, OUT1 is low
and OUT2 continues to oscillate with guaranteed off time
equal to two non-overlap delay times.
SS: A capacitor from SS to ground programs the soft start
time. During soft start, EAOUT follows the amplitude of
SS’s slowly increasing waveform until regulation is
achieved.
VDD: Chip power supply pin. VDD should be bypassed
to PGND. The -1 and -3 versions require VDD to exceed
9V to start and remain above 8.5V to continue running. A
shunt clamp from VDD to GND limits the supply voltage
to 15V. The -2 and -4 versions do not start until the shunt
clamp threshold is reached and operation continues as
long as VDD is greater than 8.5V.
0.3A drive current capability.
A
OUT1
= T
Volt-Second Product Clamp = 3.3
J
.
= 0, C
OUT2
= 0. T
A
= 0°C to 70°C for the UCC3580,
4.875
MIN
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
TYP
5
1
1
R4
5.125
MAX UNITS
20
20
CR.
mV
mV
V