UCC1580-1 Unitrode Semiconductor, UCC1580-1 Datasheet - Page 5

• Manufacturer Part Number: UCC1580-1
• Description: Single Ended Active Clamp Reset PWM
• Manufacturer: Unitrode Semiconductor

APPLICATION INFORMATION
UVLO and Startup
For self biased off-line applications, -2 and -4 versions
(UVLO on and off thresholds of 15V and 8.5V typical)
are recommended. For all other applications, -1 and -3
versions provide the lower on threshold of 9V. The IC
requires a low startup current of only 160 A when VDD
is under the UVLO threshold, enabling use of a large
trickle charge resistor (with corresponding low power
dissipation) from the input voltage. VDD has an internal
clamp at 15V which can sink up to 10mA. Measures
should be taken not to exceed this current. For -2 and
-4 versions, this clamp must be activated as an indica-
tion of reaching the UVLO on threshold. The internal
reference (REF) is brought up when the UVLO on
threshold is crossed. The startup logic ensures that
LINE and REF are above and SHTDWN is below their
respective thresholds before outputs are asserted.
LINE input is useful for monitoring actual input voltage
and shutting off the IC if it falls below a programmed
value. A resistive divider should be used to connect the
input voltage to the LINE input. This feature can protect
the power supply from excessive currents at low line
voltages.
Note: Waveforms are not to scale.
Figure 1. Output Time Relationships
5
The soft start pin provides an effective means to start
the IC in a controlled manner. An internal current of
20 A begins charging a capacitor connected to SS
once the startup conditions listed above have been
met. The voltage on SS effectively controls maximum
duty cycle on OUT1 during the charging period. OUT2
is also controlled during this period (see Figure 1). Ne-
gation of any of the startup conditions causes SS to be
immediately discharged. Internal circuitry ensures full
discharge of SS (to 0.3V) before allowing charging to
begin again, provided all the startup conditions are
again met.
Oscillator
Simplified oscillator block diagram and waveforms are
shown in Figure 3. OSC1 and OSC2 pins are used to
program the frequency and maximum duty cycle. Ca-
pacitor CT is alternately charged through R1 and dis-
charged through R2 between levels of 1V and 3.5V.
The charging and discharging equations for CT are
given by
V
V
C
C
charge
discharge
REF
3.5
4.0
e
t
e
2
t
1
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
UDG-95070-2