IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 13

• Manufacturer Part Number: IDT72285
• Description: 64k X 18 Supersync Fifo, 5.0v
• Manufacturer: Integrated Device Technology

(65,536-m) writes for the IDT72285. The offset “m” is the full offset value. The
default setting for this value is stated in the footnote of Table 1.
and (65,537-m) writes for the IDT72285, where m is the full offset value. The
default setting for this value is stated in the footnote of Table 2.
FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
and FWFT Mode), for the relevant timing information.
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
In FWFT mode, the PAF will go LOW after (32,769-m) writes for the IDT72275
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard and
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
In FWFT mode, the PAE will go LOW when there are n+1 words or less
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
PAE is synchronous and updated on the rising edge of RCLK.
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HALF-FULL FLAG (HF)
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 32,768 for the
IDT72275 and 65,536 for the IDT72285.
go LOW after (D-1/2 + 2) writes to the FIFO, where D = 32,769 for the IDT72275
and 65,537 for the IDT72285.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF will
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
17
) are data outputs for 18-bit wide data.
0
-Q
17
)
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TEMPERATURE RANGES