IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 2

• Manufacturer Part Number: IDT72285
• Description: 64k X 18 Supersync Fifo, 5.0v
• Manufacturer: Integrated Device Technology

PIN CONFIGURATIONS
DESCRIPTION (CONTINUED)
munications, data communications and other applications that need to buffer
large amounts of data.
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLK when WEN is asserted. The output port is controlled by a Read Clock
(RCLK) input and Read Enable (REN) input. Data is read from the FIFO on
every rising edge of RCLK when REN is asserted. An Output Enable (OE)
input is provided for three-state control of the outputs.
0 to f
frequency of the one clock input with respect to the other.
IDT Standard mode and First Word Fall Through (FWFT) mode.
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and enabling
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
The input port is controlled by a Write Clock (WCLK) input and a Write
The frequencies of both the RCLK and the WCLK signals may vary from
In IDT Standard mode, the first word written to an empty FIFO will not
SuperSync FIFOs are particularly appropriate for network, video, telecom-
There are two possible timing modes of operation with these devices:
MAX
with complete independence. There are no restrictions on the
PIN 1
WEN
GND
SEN
V
D17
D16
D15
D14
D13
D12
D11
D10
DC
D9
D8
D7
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
2
a rising RCLK edge, will shift the word from internal memory to the data output
lines.
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for access.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions
are selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly
For applications requiring more data storage capacity than a single FIFO
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMMERCIAL AND INDUSTRIAL
4674 drw 02
Q17
Q16
GND
Q15
Q14
V
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
TEMPERATURE RANGES
CC