IDT72285 Integrated Device Technology, IDT72285 Datasheet - Page 21

• Manufacturer Part Number: IDT72285
• Description: 64k X 18 Supersync Fifo, 5.0v
• Manufacturer: Integrated Device Technology

NOTE:
1. OE = LOW
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
D
Q
WCLK
RCLK
0
WEN
In IDT Standard mode: D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
In FWFT mode: D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
between the rising edge of RCLK and the rising edge of WCLK is less than t
0
WCLK
REN
SKEW2
PAF
RCLK
- D
WEN
- Q
REN
LD
15
LD
15
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
t
ENH
DATA IN OUTPUT
t
REGISTER
CLKH
t
CLKH
1
(2)
t
CLK
t
t
t
CLK
ENS
LDS
t
t
DS
CLKL
t
ENS
t
LDS
t
OFFSET
CLKL
SKEW2
PAE
2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
21
t
PAF
t
t
t
ENH
DH
LDH
t
LDH
t
t
ENH
A
t
ENS
t
SKEW2
(3)
OFFSET
PAF
t
ENH
D - m words in FIFO
OFFSET
PAE
t
1
DH
t
t
ENH
LDH
t
t
ENH
LDH
t
A
COMMERCIAL AND INDUSTRIAL
(2)
TEMPERATURE RANGES
2
PAF
t
PAF
). If the time
OFFSET
PAF
D-(m+1) words
in FIFO
4674 drw 19
4674 drw 17
4674 drw18
(2)