IDT71V2556S Integrated Device Technology, IDT71V2556S Datasheet - Page 20

• Manufacturer Part Number: IDT71V2556S
• Description: 128k X 36, 256k X 18 3.3v Synchronous Zbt Srams 2.5v I/o, Burst Counter Pipelined Outputs
• Manufacturer: Integrated Device Technology

NOTES:
1. Q (A
2. CE
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
internal registers in the SRAM will retain their previous state.
the actual data is presented to the SRAM.
2
timing transitions are identical but inverted to the CE
1
) represents the first output from the external address A
1
and CE
1
. D (A
2
signals. For example, when CE
2
) represents the input data to the SRAM corresponding to address A
1
and CE
2
are LOW on this waveform, CE
2
2
is HIGH.
.