IDT71V2556S Integrated Device Technology, IDT71V2556S Datasheet - Page 9

• Manufacturer Part Number: IDT71V2556S
• Description: 128k X 36, 256k X 18 3.3v Synchronous Zbt Srams 2.5v I/o, Burst Counter Pipelined Outputs
• Manufacturer: Integrated Device Technology

Synchronous Truth Table
Partial Truth Table for Writes
NOTES:
1. L = V
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
NOTES:
1. L = V
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
3. Deselect cycle is initiated when either (CE
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
5. To select the chip requires CE
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
READ
NO WRITE
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/O
WRITE BYTE 2 (I/O[8:15], I/O
WRITE BYTE 3 (I/O[16:23], I/O
WRITE BYTE 4 (I/O[24:31], I/O
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
CEN
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
tri-state two cycles after deselect is initiated.
Os remains unchanged.
H
L
L
L
L
L
L
IL
IL
, H = V
, H = V
R/W
H
X
X
X
X
X
L
IH
IH
, X = Don’t Care.
, X = Don’t Care.
Deselect
Enable
Chip
Select
Select
X
X
X
X
(5)
P1
P2
)
P3
P4
OPERATION
(2)
)
1
(2)
)
)
(2,3)
(2,3)
= L, CE
ADV/LD
X
L
L
H
H
L
H
2
1
= L, CE
, or CE
Valid
Valid
BWx
X
X
X
X
X
2
2
= H on these chip enables. Chip is deselected if any one of the chip enables is false.
(1)
is sampled high or CE
ADDRESS
External
External
Internal
Internal
USED
(1)
X
X
X
2
6.42
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
DESELECT / NOOP
9
PREVIOUS CYCLE
LOAD WRITE /
BURST WRITE
LOAD READ /
BURST READ
R/W
H
L
L
L
L
L
L
X
X
X
X
BW
Commercial and Industrial Temperature Ranges
X
L
L
H
H
H
H
1
(Advance burst counter)
(Advance burst counter)
DESELECT or STOP
CURRENT CYCLE
BURST WRITE
BURST READ
LOAD WRITE
LOAD READ
SUSPEND
BW
NOOP
X
L
H
L
H
H
H
2
(4)
(3)
BW
(2)
(2)
X
L
H
H
L
H
H
3
(3)
(2 cycles later)
Previous Value
D
Q
D
Q
HiZ
HiZ
I/O
BW
(7)
(7)
(7)
(7)
X
H
H
H
H
L
L
4875 tbl 08
4875 tbl 09
4
(3)