HT46R71D Holtek Semiconductor, HT46R71D Datasheet
HT46R71D
Related parts for HT46R71D
HT46R71D Summary of contents
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... Watchdog Timer Buzzer output Internal 12kHz RC oscillator General Description The HT46R71D is an 8-bit, high performance, RISC ar- chitecture microcontroller device specifically designed for A/D product applications that interface directly to an- alog signals and which require an LCD Interface. The advantages of low power consumption, I/O flexibil- ...
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... Block Diagram Rev. 1.00 2 HT46R71D January 9, 2006 ...
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... LCD power supply LCD driver outputs for the LCD panel segments. Bandgap voltage output pin. (for external use) Regulator output 3.3V Charge pump output (a capacitor is required to be connected) Charge pump capacitor, positive Charge pump capacitor, negative 3 HT46R71D January 9, 2006 ...
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... No load, system HALT, LCD off at HALT load, system HALT, LCD off at HALT, ADC off load, system HALT, LCD off at HALT, ADC off 5V No load, system HALT, 3V LCD on at HALT, 1/2 bias, VLCD=VDD 5V 4 HT46R71D Ta=25 C Typ. Max. Unit 5 0.8 1.5 mA 2.5 ...
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... DD 5V 350 =0. 180 Charge pump on 2.2 Charge pump off 3.7 No load 3 V =3.7V~5.5V DD Charge pump off Current 10mA V =2.4V~3.6V DD Charge pump on Current 6mA @3.3V 1.45 @3.3V 5 HT46R71D Typ. Max. Unit 0. 0. 2.1 2.2 V 2.3 2 ...
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... SST t Interrupt Pulse Width INT Note 1/f SYS SYS Rev. 1.00 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3V 5V 2.2V~5. Power-up or wake-up from HALT 1 6 HT46R71D Ta=25 C Typ. Max. Unit 4000 kHz 12 kHz 15 kHz 4000 kHz 90 180 s 65 130 1024 SYS s January 9, 2006 ...
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... Program Counter Program Counter S10~S0: Stack register bits @7~@0: PCL bits 7 HT46R71D * ...
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... CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 4 return addresses are stored). Table Location * Table Location P10~P8: Current program counter bits 8 HT46R71D * January 9, 2006 ...
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... LCD display memory. Accumulator - ACC The accumulator (ACC) is related to the ALU opera- tions also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. 9 HT46R71D January 9, 2006 ...
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... INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H oc- curs. The interrupt request flag (EIF0) and EMI bits are all cleared to disable other maskable interrupts. Function Status (0AH) Register 10 HT46R71D January 9, 2006 ...
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... During that period, if only one stack is left, and en- abling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. Function INTC 0 (0BH) Register Function INTC 1 (1EH) Register 11 HT46R71D Priority Vector 1 04H 2 08H 3 0CH ...
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... WDT. If the CLR WDT1 and CLR WDT2 option is chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT, otherwise the WDT may reset the chip due to a time-out. 12 HT46R71D 15 , the maximum 16 which will give a ...
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... PA data Register PA data Register PA.0 PA PA0/PA1 Pin Function Control 13 HT46R71D Output Function PA0=0, PA1=0 PA0=BZ, PA1=BZ PA0=0, PA1=Input PA0=BZ, PA1=Input PA0=Input, PA1=0 PA0=Input, PA1=Input January 9, 2006 ...
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... However, if the wake-up results in the next instruction execution, the execution will be per- formed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. 14 HT46R71D (system SYS January 9, 2006 ...
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... Timer/Event Counter Off Input/output Ports Input mode Stack Pointer Points to the top of the stack Rev. 1.00 Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart Reset Configuration 15 HT46R71D January 9, 2006 ...
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... HT46R71D RES Reset WDT Time-out (HALT) (HALT)* 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 0000H 0000H ...
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... T0ON/T1ON bit. The mea- sured result remains in the timer/event counter even if the activated transient occurs again. In other words, only a 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will Timer/Event Counter 0 Timer/Event Counter 1 17 HT46R71D January 9, 2006 ...
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... Width measurement mode (External clock) 00=Unused Rev. 1.00 Function /16 T0 /32 T0 /64 T0 /128 T0 ; 1=Int.RCOSC (Internal RC OSC)) SYS TMR0C (0EH) Register Function /16 T1 /32 T1 /64 T1 /128 T1 /4; 1=Int.RCOSC (Internal RC OSC)) SYS TMR1C (11H) Register 18 HT46R71D January 9, 2006 ...
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... PA0 Pad Status PA1 Pad Status Note: I input; O output D, D0, D1 Data B buzzer option don t care 19 HT46R71D January 9, 2006 ...
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... CHPRC. The CHPRC is the Charge Pump/Reg- ulator Control register, which controls the charge pump on/off, regulator on/off functions as well as setting the clock divider value to generate the clock for the charge pump. Function /16) / (CHPCKD+1) SYS CHPRC (1FH) Register 20 HT46R71D January 9, 2006 ...
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... The ADCD is the A/D Chopper clock divider register, which define the chopper clock to the ADC module. 21 HT46R71D Description is greater than 3.6V DD >3.6V less than 3. ...
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... ADRR0=0) Application hints: Application users need to choose the correctly 6/5VDSO and 1/6VDSO. (e.g. Vfull can’t be over the 5/6VDSO and Vzero can t be under 1/6VDSO) 22 HT46R71D drop under the 1/6VDSO (the C . and the Ti let the V work between C January 9, 2006 ...
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... Define the chopper clock (ADCCKEN should be enable), the suggestion clock is around 10kHz. The chopper clock define : 0: clock= (f SYS 0 ADCD0 1: clock= (f SYS 2: clock ADCD1 SYS 3: clock ADCD2 SYS 4: clock= (f SYS 5: clock= (f SYS 6: clock= (f SYS 7: clock= (f SYS 3~7 Reserved Rev. 1.00 Function ADCR (18H) Register Function /32)/1 /32)/2 /32)/4 /32)/8 /32)/16 /32)/32 /32)/64 /32)/128 ADCD (1AH) Register 23 HT46R71D January 9, 2006 ...
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... Display Memory LCD Driver Output The output number of the device LCD driver can configuration option (i.e duty or 1/3 duty). The bias type LCD driver is R type only. The LCD driver bias voltage can bias or 1/3 bias by option. 24 HT46R71D January 9, 2006 ...
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... Since a low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.00 Function MODE (09H) Register The relationship between V Note the voltage range for proper chip OPR operation at 4MHz system clock. Low Voltage Reset 25 HT46R71D and V is shown below. DD LVR January 9, 2006 ...
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... INT trigger edge selection: disable; high to low; low to high; low to high or high to low Partial-lock selection: Page0~3, Page4~6, Page7. Rev. 1.00 Options /4 SYS means the clock source selected by op HT46R71D January 9, 2006 ...
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... The resistance and capacitance for reset circuit should be designed in such a way as to ensure that V ble and remains within a valid operating voltage range before bringing RES high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.00 27 HT46R71D is sta- DD January 9, 2006 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 Description 28 HT46R71D Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 29 HT46R71D Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R71D January 9, 2006 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.00 PDF PDF PDF addr PDF PDF HT46R71D January 9, 2006 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R71D January 9, 2006 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.00 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46R71D January 9, 2006 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.00 Program Counter+1 PDF PDF PDF addr PDF PDF HT46R71D January 9, 2006 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.00 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46R71D January 9, 2006 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.00 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46R71D January 9, 2006 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.00 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46R71D January 9, 2006 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.00 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46R71D January 9, 2006 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.00 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46R71D January 9, 2006 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.00 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46R71D January 9, 2006 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R71D January 9, 2006 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.00 PDF PDF PDF HT46R71D January 9, 2006 ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 395 291 8 613 HT46R71D Max. 420 299 12 637 January 9, 2006 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 44 HT46R71D January 9, 2006 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 45 HT46R71D January 9, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 46 HT46R71D January 9, 2006 ...