HT46R71D Holtek Semiconductor, HT46R71D Datasheet - Page 21

• Manufacturer Part Number: HT46R71D
• Description: A/D with LCD Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

The CHPCKD4~0 bits are use to set the clock divider to
generate the desired clock frequency to provide the
charge pump working. The actual frequency is decide
by the following formula.
T h e A ct ua l C harg e Pump C l ock= (f
(CHPCKD+1).
The suggestion clock frequency of the charge pump is
20kHz. Application need to set the correct value to get
the desired clock frequency. e.g. for the 4MHz applica-
tion, the CHPCKD should be set to 12, and for 2MHz ap-
plication, the correct CHPCKD is 6.
The REGCEN bit in the CHPRC is the Regulator/
Charge-pump module enable/disable control bit. If this
bit is disabled, then the regulator will be disabled and the
charge pump will be also be disabled to save power.
When REGCEN = 0, the module will enter a Power
Down Mode ignoring the CHPEN setting. The ADC and
OPA will also be disabled to reduce power.
If REGCEN is set to logic 1 , the regulator will be en-
abled. If CHPEN is enabled, the charge pump will be ac-
tive and will use VDD as its input to generate the double
voltage output. This double voltage will be used as the
input of the regulator. If CHPEN is set to logic 0 , the
charge pump is disabled and the charge pump output
will be equal to the charge pump input (VDD).
Note: V
Rev. 1.00
REGCEN CHPEN
0
1
1
INT
, V
CMP
X
0
1
signal can come from different R groups which are selected by software registers.
Charge
Pump
OFF
OFF
ON
VOCHP
2 V
V
V
Pin
DD
DD
DD
Regulator
S Y S
OFF
ON
ON
/16 ) /
21
Hi-Impedance
VOREG Pin OPA ADC
Users need to take care of the V
is under 3.6V, then CHPEN should be set to 1 to enable
the charge pump, otherwise CHPEN should be set to
zero. If the Charge pump is disabled and V
3.6V then the output voltage of the regulator will not be
guaranteed.
ADC - Dual Slope
A Dual Slope A/D converter is implemented in this
microcontroller. The dual slope module includes an Op-
erational Amplifier and a buffer for the amplification of
differential signals, an Integrator and a comparator for
the main dual slope AD converter.
In addition, there is also an integrated band gap voltage
generator for the 1.5V low temperature sensitive refer-
ence voltage. This reference voltage is used as the zero
adjustment and for a single end type reference voltage.
There are 2 special function registers related to this
block including: ADCR and ADCD. The ADCR register
is the A/D control register, which controls the ADC block
power on/off, the chopper clock on/off, the charge/dis-
charge control and is also used to read out the compara-
tor output status. The ADCD is the A/D Chopper clock
divider register, which define the chopper clock to the
ADC module.
3.3V
3.3V
Disable
Active
Active
The whole module is disable,
OPA/ADC will lose the Power
Use for V
(V
Use for V
(V
DD
DD
>3.6V)
=2.2V~3.6V)
DD
DD
Description
DD
voltage, if the voltage
is greater than 3.6V
is less than 3.6V
HT46R71D
January 9, 2006
DD
is under