HT46R74D-1 Holtek Semiconductor, HT46R74D-1 Datasheet - Page 23

• Manufacturer Part Number: HT46R74D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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The suggested charge pump clock frequency is 20kHz.
The application needs to set the correct value to get the
desired clock frequency. For a 4MHz application, the
CHPCKD bits should be set to the decimal value 11, and
for a 2MHz application, the bits should be set to 5.
The REGCEN bit in the CHPRC register is the Regula-
tor/Charge-pump module enable/disable control bit. If
this bit is disabled, then the regulator will be disabled
and the charge pump will be also be disabled to save
power. When REGCEN = 0, the module will enter the
Power Down Mode ignoring the CHPEN setting. The
ADC and OPA will also be disabled to reduce power.
If REGCEN is set to 1 , the regulator will be enabled. If
the CHPEN bit is enabled, the charge pump will be ac-
tive and will use VDD as its input to generate the double
voltage output. This double voltage will then be used as
the input voltage for the regulator. If CHPEN is set to 0 ,
the charge pump is disabled and the charge pump out-
put will be equal to the charge pump input, VDD.
It is necessary to carefully manage the V
the voltage is less than 3.6V, then CHPEN should be set
to 1 to enable the charge pump, otherwise CHPEN
should be set to zero. If the Charge pump is disabled
and V
regulator will not be guaranteed.
Rev. 1.10
REGCEN CHPEN
Bit No.
3~7
0
1
2
0
1
1
DD
is less than 3.6V then the output voltage of the
CHPCKD0~
CHPCKD4
REGCEN
BGPQST
CHPEN
Label
X
0
1
Charge
Pump
OFF
OFF
ON
Enable/disable Regulator/Charge-Pump module. (1=enable; 0=disable)
Charge Pump Enable/disable setting. (1=enable; 0=disable)
Note: this bit will be ignored if the REGCEN bit is disabled
Bandgap quick start-up function
0: R short, quick start up
1: R off, normal RC filter mode
Each time REGCEN changes from 0 to 1, that is when the regulator turns on, this bit should
be set to 0 and then set to 1 to ensure a quick start up. The minimum time to keep the bit low
should be about 2ms.
Charge pump clock divider. These 5 bits form a clock divider with a division ratio range of 1
to 32. Charge Pump clock = (f
VOCHP
2 V
V
V
Pin
DD
DD
DD
DD
Regulator
voltage. If
CHPRC (1FH) Register
OFF
ON
ON
SYS
23
Hi-Impedance
VOREG Pin OPA ADC
/16) / (CHPCKD+1)
ADC - Dual Slope
A Dual Slope A/D converter is implemented within the
microcontroller. The dual slope module includes an Op-
erational Amplifier and a buffer for the amplification of
differential signals and an Integrator and comparator for
the main dual slope AD converter.
There are 3 special function registers related to the ADC
function known as ADCR, ADCD and EADCR. The
ADCR register is the A/D control register, which controls
the ADC block power on/off, the chopper clock on/off,
the charge/discharge control and is also used to read
out the comparator output status. The ADCD register is
the A/D Chopper clock divider register, which defines
the chopper clock to the ADC module. The EADCR reg-
ister is the enhanced A/D control register, which defines
the Auto Mode Dual Slope ADC function.
The ADPWREN bit in the ADCR register, is used to con-
trol the ADC module on/off function. The ADCCKEN bit
in the ADCR register is used to control the chopper clock
on/off function. When the ADCCKEN bit is set to 1 it
will enable the Chopper clock, with the clock frequency
defined by the ADCD registers. The ADC module in-
cludes the OPA, buffer, integrator and comparator, how-
ever the Bandgap voltage generator is independent of
this module. It will be automatically enabled when the
3.3V
3.3V
Function
Disable
Active
Active
Complete module is disabled,
OPA/ADC will have no Power
Used when V
3.6V
Use whefor V
3.6V (V
DD
Description
=2.2V~3.6V)
HT46R74D-1
DD
January 11, 2007
DD
is greater than
is less than