HT46R74D-1 Holtek Semiconductor, HT46R74D-1 Datasheet - Page 24

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HT46R74D-1

Manufacturer Part Number
HT46R74D-1
Description
Dual Slope A/D Type MCU
Manufacturer
Holtek Semiconductor
Datasheet
www.DataSheet4U.com
Note: The V
regulator is enabled, and also be disabled when the reg-
ulator is disabled. The application program should en-
able the related power to permit them to function and
disable them when idle to conserve power. The
charge/discharge control bits, ADDISCH1~ ADDISCH0,
are used to control the Dual slope circuit charging and
discharging behavior. The ADCMPO bit is read only for
the comparator output, while the ADINTM bits can set
the ADCMPO trigger mode for interrupt generation.
The following descriptions are based on the fact that
ADRR0=0
Rev. 1.10
INT
, V
CMP
signals can come from different R groups which are selected by software registers.
24
The amplifier and buffer combination, form a differential
input pre-amplifier which amplifies the sensor input
signal.
The combination of the Integrator, the comparator, the
resistor Rds, between DSRR and DSRC and the capaci-
tor Cds, between DSRC and DSCC form the main body
of the Dual slope ADC.
The Integrator integrates the output voltage increase or
decrease and is controlled by the Switch Circuit - refer
to the block diagram. The charge and discharge curves
are illustrated by the following.
The comparator will switch the state from high to low
when VC, which is the DSCC pin voltage,drops to less
than 1/6 VDSO.
In general applications, the application program will
switch the ADC to the charging mode for a fixed time
called Ti, which is the integrating time. It will then switch
to the dis-charging mode and wait for V
than 1/6VDSO. At this point the comparator will change
HT46R74D-1
January 11, 2007
c
to drop to less

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