HT48E10 Holtek Semiconductor, HT48E10 Datasheet - Page 10

• Manufacturer Part Number: HT48E10
• Description: I/O Type 8-Bit MTP MCU
• Manufacturer: Holtek Semiconductor

Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by op-
tions. If the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 65 s at 5V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 18.4ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2, WS1,
and WS0 are all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.4s at 5V seconds. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by an external logic. The
high nibble and bit 3 of the WDTS are reserved for user s
defined flags, which can be used to indicate some speci-
fied status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
Rev. 1.50
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WDTS (09H) Register
WS0
0
1
0
1
0
1
0
1
Division Ratio
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
Watchdog Timer
10
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset
and only the Program Counter and SP are reset to zero.
To clear the WDT contents (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a HALT in-
struction. The software instruction includes CLR WDT
and the other set
these two types of instructions, only one can be active
depending on the option
option . If the CLR WDT is selected (i.e. CLRWDT
times is equal to one), any execution of the CLR WDT
instruction will clear the WDT. In the case that CLR
WDT1 and CLR WDT2 are chosen (i.e. CLRWDT
times is equal to two), these two instructions must be ex-
ecuted to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the CLR WDT instruction and is set when exe-
cuting the HALT instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP; the others remain
in their original status.
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
CLR WDT1 and CLR WDT2 . Of
CLR WDT times selection
October 31, 2006
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HT48E10